Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6

[linux-2.6-omap-h63xx.git] / include / asm-ppc / reg_booke.h

diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 602fbadeaf480cff1769496e9e37e3796356e7fa..91e96af88bd8631ad51441f2132e049669cc66ad 100644 (file)
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -10,40 +10,6 @@
 #define __ASM_PPC_REG_BOOKE_H__
 
 #ifndef __ASSEMBLY__
-/* Device Control Registers */
-void __mtdcr(int reg, unsigned int val);
-unsigned int __mfdcr(int reg);
-#define mfdcr(rn)                                              \
-       ({unsigned int rval;                                    \
-       if (__builtin_constant_p(rn))                           \
-               asm volatile("mfdcr %0," __stringify(rn)        \
-                             : "=r" (rval));                   \
-       else                                                    \
-               rval = __mfdcr(rn);                             \
-       rval;})
-
-#define mtdcr(rn, v)                                           \
-do {                                                           \
-       if (__builtin_constant_p(rn))                           \
-               asm volatile("mtdcr " __stringify(rn) ",%0"     \
-                             : : "r" (v));                     \
-       else                                                    \
-               __mtdcr(rn, v);                                 \
-} while (0)
-
-/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
-#define mfdcri(base, reg)                      \
-({                                             \
-       mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
-       mfdcr(base ## _CFGDATA);                        \
-})
-
-#define mtdcri(base, reg, data)                        \
-do {                                           \
-       mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
-       mtdcr(base ## _CFGDATA, data);          \
-} while (0)
-
 /* Performance Monitor Registers */
 #define mfpmr(rn)      ({unsigned int rval; \
                        asm volatile("mfpmr %0," __stringify(rn) \
@@ -241,7 +207,7 @@ do {                                                \
 #define        CCR1_TCS        0x00000080 /* Timer Clock Select */
 
 /* Bit definitions for the MCSR. */
-#ifdef CONFIG_440A
+#ifdef CONFIG_4xx
 #define MCSR_MCS       0x80000000 /* Machine Check Summary */
 #define MCSR_IB                0x40000000 /* Instruction PLB Error */
 #define MCSR_DRB       0x20000000 /* Data Read PLB Error */
@@ -252,32 +218,6 @@ do {                                               \
 #define MCSR_DCFP      0x01000000 /* D-Cache Flush Parity Error */
 #define MCSR_IMPE      0x00800000 /* Imprecise Machine Check Exception */
 #endif
-#ifdef CONFIG_E500
-#define MCSR_MCP       0x80000000UL /* Machine Check Input Pin */
-#define MCSR_ICPERR    0x40000000UL /* I-Cache Parity Error */
-#define MCSR_DCP_PERR  0x20000000UL /* D-Cache Push Parity Error */
-#define MCSR_DCPERR    0x10000000UL /* D-Cache Parity Error */
-#define MCSR_GL_CI     0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
-#define MCSR_BUS_IAERR         0x00000080UL /* Instruction Address Error */
-#define MCSR_BUS_RAERR         0x00000040UL /* Read Address Error */
-#define MCSR_BUS_WAERR         0x00000020UL /* Write Address Error */
-#define MCSR_BUS_IBERR         0x00000010UL /* Instruction Data Error */
-#define MCSR_BUS_RBERR         0x00000008UL /* Read Data Bus Error */
-#define MCSR_BUS_WBERR         0x00000004UL /* Write Data Bus Error */
-#define MCSR_BUS_IPERR         0x00000002UL /* Instruction parity Error */
-#define MCSR_BUS_RPERR         0x00000001UL /* Read parity Error */
-#endif
-#ifdef CONFIG_E200
-#define MCSR_MCP       0x80000000UL /* Machine Check Input Pin */
-#define MCSR_CP_PERR   0x20000000UL /* Cache Push Parity Error */
-#define MCSR_CPERR     0x10000000UL /* Cache Parity Error */
-#define MCSR_EXCP_ERR  0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
-                                       fetch for an exception handler */
-#define MCSR_BUS_IRERR         0x00000010UL /* Read Bus Error on instruction fetch*/
-#define MCSR_BUS_DRERR         0x00000008UL /* Read Bus Error on data load */
-#define MCSR_BUS_WRERR         0x00000004UL /* Write Bus Error on buffered
-                                       store or cache line push */
-#endif
 
 /* Bit definitions for the DBSR. */
 /*
@@ -317,7 +257,7 @@ do {                                                \
 #define ESR_IMCB       0x20000000      /* Instr. Machine Check - Bus error */
 #define ESR_IMCT       0x10000000      /* Instr. Machine Check - Timeout */
 #define ESR_PIL                0x08000000      /* Program Exception - Illegal */
-#define ESR_PPR                0x04000000      /* Program Exception - Priveleged */
+#define ESR_PPR                0x04000000      /* Program Exception - Privileged */
 #define ESR_PTR                0x02000000      /* Program Exception - Trap */
 #define ESR_FP         0x01000000      /* Floating Point Operation */
 #define ESR_DST                0x00800000      /* Storage Exception - Data miss */