Merge branch 'drm-patches' of ssh://master.kernel.org/pub/scm/linux/kernel/git/airlie...

[linux-2.6-omap-h63xx.git] / include / asm-sh / system.h

diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 4a6a19f4f8a47f291c92fd36ba36aeb8aa400c31..7c75045ae22b419da64e094f53bf35feb79484a0 100644 (file)
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -8,7 +8,12 @@
 
 #include <linux/irqflags.h>
 #include <linux/compiler.h>
+#include <linux/linkage.h>
 #include <asm/types.h>
+#include <asm/ptrace.h>
+
+struct task_struct *__switch_to(struct task_struct *prev,
+                               struct task_struct *next);
 
 /*
  *     switch_to() should switch tasks to task nr n, first
@@ -81,16 +86,6 @@ static inline void sched_cacheflush(void)
 }
 #endif
 
-static inline unsigned long tas(volatile int *m)
-{
-       unsigned long retval;
-
-       __asm__ __volatile__ ("tas.b    @%1\n\t"
-                             "movt     %0"
-                             : "=r" (retval): "r" (m): "t", "memory");
-       return retval;
-}
-
 /*
  * A brief note on ctrl_barrier(), the control register write barrier.
  *
@@ -131,7 +126,7 @@ static inline unsigned long tas(volatile int *m)
 #define smp_read_barrier_depends()     do { } while(0)
 #endif
 
-#define set_mb(var, value) do { xchg(&var, value); } while (0)
+#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
 
 /*
  * Jump to P2 area.
@@ -255,6 +250,8 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
                                    (unsigned long)_n_, sizeof(*(ptr))); \
   })
 
+extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
+
 extern void *set_exception_table_vec(unsigned int vec, void *handler);
 
 static inline void *set_exception_table_evt(unsigned int evt, void *handler)
@@ -262,6 +259,15 @@ static inline void *set_exception_table_evt(unsigned int evt, void *handler)
        return set_exception_table_vec(evt >> 5, handler);
 }
 
+/*
+ * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
+ */
+#ifdef CONFIG_CPU_SH2A
+extern unsigned int instruction_size(unsigned int insn);
+#else
+#define instruction_size(insn) (2)
+#endif
+
 /* XXX
  * disable hlt during certain critical i/o operations
  */
@@ -269,6 +275,16 @@ static inline void *set_exception_table_evt(unsigned int evt, void *handler)
 void disable_hlt(void);
 void enable_hlt(void);
 
+void default_idle(void);
+
+asmlinkage void break_point_trap(void);
+asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5,
+                                  unsigned long r6, unsigned long r7,
+                                  struct pt_regs __regs);
+asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5,
+                                unsigned long r6, unsigned long r7,
+                                struct pt_regs __regs);
+
 #define arch_align_stack(x) (x)
 
 #endif