X-Git-Url: http://pilppa.org/gitweb/?a=blobdiff_plain;f=arch%2Fppc%2Fkernel%2Fcpu_setup_power4.S;h=6a674e834eebbf65eccbaf25ff698cceccec81a4;hb=ccaa36f73544163ef6e15eb29a620130755f6001;hp=7e4fbb65372405d5d22482197518436859f3e6f9;hpb=165415f700b0c77fa1f8db6198f48582639adf78;p=linux-2.6-omap-h63xx.git

diff --git a/arch/ppc/kernel/cpu_setup_power4.S b/arch/ppc/kernel/cpu_setup_power4.S
index 7e4fbb65372..6a674e834ee 100644
--- a/arch/ppc/kernel/cpu_setup_power4.S
+++ b/arch/ppc/kernel/cpu_setup_power4.S
@@ -9,7 +9,6 @@
  *
  */
 
-#include <linux/config.h>
 #include <asm/processor.h>
 #include <asm/page.h>
 #include <asm/ppc_asm.h>
@@ -63,8 +62,6 @@ _GLOBAL(__970_cpu_preinit)
 	isync
 	blr
 
-_GLOBAL(__setup_cpu_power4)
-	blr
 _GLOBAL(__setup_cpu_ppc970)
 	mfspr	r0,SPRN_HID0
 	li	r11,5			/* clear DOZE and SLEEP */
@@ -88,10 +85,10 @@ _GLOBAL(__setup_cpu_ppc970)
 #define CS_SIZE		32
 
 	.data
-	.balign	L1_CACHE_LINE_SIZE
+	.balign	L1_CACHE_BYTES
 cpu_state_storage:	
 	.space	CS_SIZE
-	.balign	L1_CACHE_LINE_SIZE,0
+	.balign	L1_CACHE_BYTES,0
 	.text
 	
 /* Called in normal context to backup CPU 0 state. This