X-Git-Url: http://pilppa.org/gitweb/?a=blobdiff_plain;f=arch%2Fx86%2Fmm%2Fpageattr.c;h=9c4294986af779ed62ab088af0dae0f0048eb0c9;hb=6e15cf04860074ad032e88c306bea656bbdd0f22;hp=8253bc97587e4950e2c2ea3170da767245ac825f;hpb=ecc25fbd6b9e07b33895c61ddf84006b00f55d99;p=linux-2.6-omap-h63xx.git

diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 8253bc97587..9c4294986af 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -522,6 +522,17 @@ static int split_large_page(pte_t *kpte, unsigned long address)
 	 * primary protection behavior:
 	 */
 	__set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
+
+	/*
+	 * Intel Atom errata AAH41 workaround.
+	 *
+	 * The real fix should be in hw or in a microcode update, but
+	 * we also probabilistically try to reduce the window of having
+	 * a large TLB mixed with 4K TLBs while instruction fetches are
+	 * going on.
+	 */
+	__flush_tlb_all();
+
 	base = NULL;
 
 out_unlock: