X-Git-Url: http://pilppa.org/gitweb/?a=blobdiff_plain;f=drivers%2Fnet%2Fmv643xx_eth.h;h=33c5fafdbbd3f2cfae431b9fa03d15f172df0a9b;hb=6fa0cb1141da80eed4f86155fb51931bc1c31888;hp=7754d1974b9e0ac63ab7642cc0209e9093cabbc2;hpb=ba93c6297b9cfad5a70b5e5ed13c9dbead6601d3;p=linux-2.6-omap-h63xx.git

diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h
index 7754d1974b9..33c5fafdbbd 100644
--- a/drivers/net/mv643xx_eth.h
+++ b/drivers/net/mv643xx_eth.h
@@ -42,13 +42,23 @@
 #define MAX_DESCS_PER_SKB	1
 #endif
 
+/*
+ * The MV643XX HW requires 8-byte alignment.  However, when I/O
+ * is non-cache-coherent, we need to ensure that the I/O buffers
+ * we use don't share cache lines with other data.
+ */
+#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_NOT_COHERENT_CACHE)
+#define ETH_DMA_ALIGN		L1_CACHE_BYTES
+#else
+#define ETH_DMA_ALIGN		8
+#endif
+
 #define ETH_VLAN_HLEN		4
 #define ETH_FCS_LEN		4
-#define ETH_DMA_ALIGN		8	/* hw requires 8-byte alignment */
-#define ETH_HW_IP_ALIGN		2	/* hw aligns IP header */
+#define ETH_HW_IP_ALIGN		2		/* hw aligns IP header */
 #define ETH_WRAPPER_LEN		(ETH_HW_IP_ALIGN + ETH_HLEN + \
-				ETH_VLAN_HLEN + ETH_FCS_LEN)
-#define ETH_RX_SKB_SIZE		((dev->mtu + ETH_WRAPPER_LEN + 7) & ~0x7)
+					ETH_VLAN_HLEN + ETH_FCS_LEN)
+#define ETH_RX_SKB_SIZE		(dev->mtu + ETH_WRAPPER_LEN + ETH_DMA_ALIGN)
 
 #define ETH_RX_QUEUES_ENABLED	(1 << 0)	/* use only Q0 for receive */
 #define ETH_TX_QUEUES_ENABLED	(1 << 0)	/* use only Q0 for transmit */
@@ -248,7 +258,7 @@ struct pkt_info {
 	struct sk_buff *return_info;	/* User resource return information */
 };
 
-/* Ethernet port specific infomation */
+/* Ethernet port specific information */
 
 struct mv643xx_mib_counters {
 	u64 good_octets_received;