*************************************************************************/
 
 #define DRV_NAME       "pcnet32"
-#ifdef CONFIG_PCNET32_NAPI
-#define DRV_VERSION    "1.34-NAPI"
-#else
-#define DRV_VERSION    "1.34"
-#endif
-#define DRV_RELDATE    "14.Aug.2007"
+#define DRV_VERSION    "1.35"
+#define DRV_RELDATE    "21.Apr.2008"
 #define PFX            DRV_NAME ": "
 
 static const char *const version =
 
 static void pcnet32_netif_stop(struct net_device *dev)
 {
-#ifdef CONFIG_PCNET32_NAPI
        struct pcnet32_private *lp = netdev_priv(dev);
-#endif
+
        dev->trans_start = jiffies;
-#ifdef CONFIG_PCNET32_NAPI
        napi_disable(&lp->napi);
-#endif
        netif_tx_disable(dev);
 }
 
 static void pcnet32_netif_start(struct net_device *dev)
 {
-#ifdef CONFIG_PCNET32_NAPI
        struct pcnet32_private *lp = netdev_priv(dev);
        ulong ioaddr = dev->base_addr;
        u16 val;
-#endif
+
        netif_wake_queue(dev);
-#ifdef CONFIG_PCNET32_NAPI
        val = lp->a.read_csr(ioaddr, CSR3);
        val &= 0x00ff;
        lp->a.write_csr(ioaddr, CSR3, val);
        napi_enable(&lp->napi);
-#endif
 }
 
 /*
        rc = 1;                 /* default to fail */
 
        if (netif_running(dev))
-#ifdef CONFIG_PCNET32_NAPI
                pcnet32_netif_stop(dev);
-#else
-               pcnet32_close(dev);
-#endif
 
        spin_lock_irqsave(&lp->lock, flags);
        lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
        x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
        a->write_bcr(ioaddr, 32, (x & ~0x0002));
 
-#ifdef CONFIG_PCNET32_NAPI
        if (netif_running(dev)) {
                pcnet32_netif_start(dev);
                pcnet32_restart(dev, CSR0_NORMAL);
                lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
        }
        spin_unlock_irqrestore(&lp->lock, flags);
-#else
-       if (netif_running(dev)) {
-               spin_unlock_irqrestore(&lp->lock, flags);
-               pcnet32_open(dev);
-       } else {
-               pcnet32_purge_rx_ring(dev);
-               lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
-               spin_unlock_irqrestore(&lp->lock, flags);
-       }
-#endif
 
        return (rc);
 }                              /* end pcnet32_loopback_test  */
        }
        dev->stats.rx_bytes += skb->len;
        skb->protocol = eth_type_trans(skb, dev);
-#ifdef CONFIG_PCNET32_NAPI
        netif_receive_skb(skb);
-#else
-       netif_rx(skb);
-#endif
        dev->last_rx = jiffies;
        dev->stats.rx_packets++;
        return;
        return must_restart;
 }
 
-#ifdef CONFIG_PCNET32_NAPI
 static int pcnet32_poll(struct napi_struct *napi, int budget)
 {
        struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
        }
        return work_done;
 }
-#endif
 
 #define PCNET32_REGS_PER_PHY   32
 #define PCNET32_MAX_PHYS       32
        /* napi.weight is used in both the napi and non-napi cases */
        lp->napi.weight = lp->rx_ring_size / 2;
 
-#ifdef CONFIG_PCNET32_NAPI
        netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
-#endif
 
        if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
            ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
                goto err_free_ring;
        }
 
-#ifdef CONFIG_PCNET32_NAPI
        napi_enable(&lp->napi);
-#endif
 
        /* Re-initialize the PCNET32, and start it when done. */
        lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
                                       dev->name, csr0);
                        /* unlike for the lance, there is no restart needed */
                }
-#ifdef CONFIG_PCNET32_NAPI
                if (netif_rx_schedule_prep(dev, &lp->napi)) {
                        u16 val;
                        /* set interrupt masks */
                        __netif_rx_schedule(dev, &lp->napi);
                        break;
                }
-#else
-               pcnet32_rx(dev, lp->napi.weight);
-               if (pcnet32_tx(dev)) {
-                       /* reset the chip to clear the error condition, then restart */
-                       lp->a.reset(ioaddr);
-                       lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
-                       pcnet32_restart(dev, CSR0_START);
-                       netif_wake_queue(dev);
-               }
-#endif
                csr0 = lp->a.read_csr(ioaddr, CSR0);
        }
 
-#ifndef CONFIG_PCNET32_NAPI
-       /* Set interrupt enable. */
-       lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
-#endif
-
        if (netif_msg_intr(lp))
                printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
                       dev->name, lp->a.read_csr(ioaddr, CSR0));
        del_timer_sync(&lp->watchdog_timer);
 
        netif_stop_queue(dev);
-#ifdef CONFIG_PCNET32_NAPI
        napi_disable(&lp->napi);
-#endif
 
        spin_lock_irqsave(&lp->lock, flags);