PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
 #define COMMON_USER_POWER5_PLUS        (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
                                 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
+#define COMMON_USER_POWER6     (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
+                                PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
 #define COMMON_USER_BOOKE      (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
                                 PPC_FEATURE_BOOKE)
 
                .oprofile_type          = PPC_OPROFILE_POWER4,
                .platform               = "power5+",
        },
+       {       /* Power6 */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x003e0000,
+               .cpu_name               = "POWER6",
+               .cpu_features           = CPU_FTRS_POWER6,
+               .cpu_user_features      = COMMON_USER_POWER6,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .num_pmcs               = 6,
+               .cpu_setup              = __setup_cpu_power4,
+               .oprofile_cpu_type      = "ppc64/power6",
+               .oprofile_type          = PPC_OPROFILE_POWER4,
+               .platform               = "power6",
+       },
        {       /* Cell Broadband Engine */
                .pvr_mask               = 0xffff0000,
                .pvr_value              = 0x00700000,
 
  */
 static unsigned char ibm_architecture_vec[] = {
        W(0xfffe0000), W(0x003a0000),   /* POWER5/POWER5+ */
+       W(0xffff0000), W(0x003e0000),   /* POWER6 */
        W(0xfffffffe), W(0x0f000001),   /* all 2.04-compliant and earlier */
        5 - 1,                          /* 5 option vectors */
 
 
 #define PPC_FEATURE_BOOKE              0x00008000
 #define PPC_FEATURE_SMT                        0x00004000
 #define PPC_FEATURE_ICACHE_SNOOP       0x00002000
+#define PPC_FEATURE_ARCH_2_05          0x00001000
 
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
            CPU_FTR_MMCRA | CPU_FTR_SMT | \
            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
            CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR)
+#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
+           CPU_FTR_MMCRA | CPU_FTR_SMT | \
+           CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+           CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE)
 #define CPU_FTRS_CELL  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 #ifdef __powerpc64__
 #define CPU_FTRS_POSSIBLE      \
            (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
-           CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL | \
-            CPU_FTR_CI_LARGE_PAGE)
+           CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
+           CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)
 #else
 enum {
        CPU_FTRS_POSSIBLE =
 #ifdef __powerpc64__
 #define CPU_FTRS_ALWAYS                \
            (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
-           CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL & \
-           CPU_FTRS_POSSIBLE)
+           CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
+           CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)
 #else
 enum {
        CPU_FTRS_ALWAYS =