[MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq

Further incorporation of generic irq framework.  Replacing __do_IRQ()
by proper flow handler would make the irq handling path a bit simpler
and faster.

* use generic_handle_irq() instead of __do_IRQ().
* use handle_level_irq for obvious level-type irq chips.
* use handle_percpu_irq for irqs marked as IRQ_PER_CPU.
* setup .eoi routine for irq chips possibly used with handle_percpu_irq.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index d0af08bdbb4e752f0bb1802914bf3138a3a0caa5..269b22b34313212191a70fba6154477f79318cb8 100644 (file)
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -103,9 +103,11 @@ void __init init_ioasic_irqs(int base)
        fast_iob();
 
        for (i = base; i < base + IO_INR_DMA; i++)
-               set_irq_chip(i, &ioasic_irq_type);
+               set_irq_chip_and_handler(i, &ioasic_irq_type,
+                                        handle_level_irq);
        for (; i < base + IO_IRQ_LINES; i++)
-               set_irq_chip(i, &ioasic_dma_irq_type);
+               set_irq_chip_and_handler(i, &ioasic_dma_irq_type,
+                                        handle_level_irq);
 
        ioasic_irq_base = base;
 }

diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index c761d97787ec01847d3e787ad634f8818429a33f..5a9be4c93584e68a7c70e95775e5ef01aa23c97a 100644 (file)
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -85,7 +85,7 @@ void __init init_kn02_irqs(int base)
        iob();
 
        for (i = base; i < base + KN02_IRQ_LINES; i++)
-               set_irq_chip(i, &kn02_irq_type);
+               set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
 
        kn02_irq_base = base;
 }

diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
index bf1b83ba925e328da8c922c9f82667b27a76f2c1..59b98299c89694ac3a04fa6fbb23edab0f76066c 100644 (file)
--- a/arch/mips/emma2rh/common/irq_emma2rh.c
+++ b/arch/mips/emma2rh/common/irq_emma2rh.c
@@ -76,7 +76,8 @@ void emma2rh_irq_init(u32 irq_base)
        u32 i;
 
        for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++)
-               set_irq_chip(i, &emma2rh_irq_controller);
+               set_irq_chip_and_handler(i, &emma2rh_irq_controller,
+                                        handle_level_irq);
 
        emma2rh_irq_base = irq_base;
 }

diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
index 8e5f08a4245d8c2b099817e63023441ba445362d..3ac4e405ecdce6253065e5d6f8e464672da516bf 100644 (file)
--- a/arch/mips/emma2rh/markeins/irq_markeins.c
+++ b/arch/mips/emma2rh/markeins/irq_markeins.c
@@ -68,7 +68,8 @@ void emma2rh_sw_irq_init(u32 irq_base)
        u32 i;
 
        for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
-               set_irq_chip(i, &emma2rh_sw_irq_controller);
+               set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller,
+                                        handle_level_irq);
 
        emma2rh_sw_irq_base = irq_base;
 }

diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 4bbb6cb08d6ec7904a3003f3ebfcc433c526465c..5c4f50cdf1576e59ff4efa4bc907bdc87d4c65f8 100644 (file)
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -59,7 +59,7 @@ void __init init_r4030_ints(void)
        int i;
 
        for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++)
-               set_irq_chip(i, &r4030_irq_type);
+               set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
 
        r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
        r4030_read_reg16(JAZZ_IO_IRQ_SOURCE);           /* clear pending IRQs */

diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index e1880b27381bbe55a70f87a2b38d3222d0214a11..bcaad6696082480c114c5cbc57e674e9ed2a3ea7 100644 (file)
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -117,6 +117,7 @@ struct irq_chip msc_levelirq_type = {
        .mask = mask_msc_irq,
        .mask_ack = level_mask_and_ack_msc_irq,
        .unmask = unmask_msc_irq,
+       .eoi = unmask_msc_irq,
        .end = end_msc_irq,
 };
 
@@ -126,6 +127,7 @@ struct irq_chip msc_edgeirq_type = {
        .mask = mask_msc_irq,
        .mask_ack = edge_mask_and_ack_msc_irq,
        .unmask = unmask_msc_irq,
+       .eoi = unmask_msc_irq,
        .end = end_msc_irq,
 };
 

diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 5012b9df1b5a1bf1daba5f84de65846026dee3f4..6cfb31cafde2806d387f7736fa6eeb636d84dd85 100644 (file)
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -114,7 +114,8 @@ void __init mv64340_irq_init(unsigned int base)
        int i;
 
        for (i = base; i < base + 64; i++)
-               set_irq_chip(i, &mv64340_irq_type);
+               set_irq_chip_and_handler(i, &mv64340_irq_type,
+                                        handle_level_irq);
 
        irq_base = base;
 }

diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 6a297e3b8899166eb19ca9eff6d79942b92f052e..ddcc2a5f8a066d6cf55525e302597f8500d16871 100644 (file)
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -51,7 +51,8 @@ void __init rm7k_cpu_irq_init(int base)
        clear_c0_intcontrol(0x00000f00);                /* Mask all */
 
        for (i = base; i < base + 4; i++)
-               set_irq_chip(i, &rm7k_irq_controller);
+               set_irq_chip_and_handler(i, &rm7k_irq_controller,
+                                        handle_level_irq);
 
        irq_base = base;
 }

diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 977538445cf3f996b52a82ef8e36d4fe4ca2789a..ba6440c88abd3a7b3e3e400cf50bb95c7856818c 100644 (file)
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -117,10 +117,12 @@ void __init rm9k_cpu_irq_init(int base)
        clear_c0_intcontrol(0x0000f000);                /* Mask all */
 
        for (i = base; i < base + 4; i++)
-               set_irq_chip(i, &rm9k_irq_controller);
+               set_irq_chip_and_handler(i, &rm9k_irq_controller,
+                                        handle_level_irq);
 
        rm9000_perfcount_irq = base + 1;
-       set_irq_chip(rm9000_perfcount_irq, &rm9k_perfcounter_irq);
+       set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
+                                handle_level_irq);
 
        irq_base = base;
 }

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 3b7cfa407e87394f669d9a9cae5bdd62724a2c94..be5ac23d3812caefbe18948da35df0a06e502551 100644 (file)
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -62,6 +62,7 @@ static struct irq_chip mips_cpu_irq_controller = {
        .mask           = mask_mips_irq,
        .mask_ack       = mask_mips_irq,
        .unmask         = unmask_mips_irq,
+       .eoi            = unmask_mips_irq,
        .end            = mips_cpu_irq_end,
 };
 
@@ -104,6 +105,7 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
        .mask           = mask_mips_mt_irq,
        .mask_ack       = mips_mt_cpu_irq_ack,
        .unmask         = unmask_mips_mt_irq,
+       .eoi            = unmask_mips_mt_irq,
        .end            = mips_mt_cpu_irq_end,
 };
 
@@ -124,7 +126,8 @@ void __init mips_cpu_irq_init(int irq_base)
                        set_irq_chip(i, &mips_mt_cpu_irq_controller);
 
        for (i = irq_base + 2; i < irq_base + 8; i++)
-               set_irq_chip(i, &mips_cpu_irq_controller);
+               set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
+                                        handle_level_irq);
 
        mips_cpu_irq_base = irq_base;
 }

diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 2ac19a6cbf68d61d6c2b2f6e93055c8c250e0d08..1ee689c0e0c991b9537ec6b170b59614b9fd4f89 100644 (file)
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -278,7 +278,9 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
 
        /* need to mark IPI's as IRQ_PER_CPU */
        irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
+       set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
        irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
+       set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
 }
 
 /*

diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 3b78caf112f5d5c361bdb82fb0c1f455fb9a9cf2..802febed7df595016087cb90e106e06030835f41 100644 (file)
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1009,6 +1009,7 @@ void setup_cross_vpe_interrupts(void)
        setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
 
        irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU;
+       set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
 }
 
 /*

diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index cac82afe5eb422959290738e7fe027cbeecf853a..4a84a7beac531fb50c2e94e5b176b672bc440f89 100644 (file)
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -133,5 +133,5 @@ void __init arch_init_irq(void)
        }
 
        for (i = 0; i <= LASATINT_END; i++)
-               set_irq_chip(i, &lasat_irq_type);
+               set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
 }

diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 7c710040d3f1c16f88b1fab7f741ea9b561adb44..43dba6ce6603be07de661fd6d80319b1bb5dc2fb 100644 (file)
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -74,6 +74,7 @@ static struct irq_chip atlas_irq_type = {
        .mask = disable_atlas_irq,
        .mask_ack = disable_atlas_irq,
        .unmask = enable_atlas_irq,
+       .eoi = enable_atlas_irq,
        .end = end_atlas_irq,
 };
 
@@ -207,7 +208,7 @@ static inline void init_atlas_irqs (int base)
        atlas_hw0_icregs->intrsten = 0xffffffff;
 
        for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
-               set_irq_chip(i, &atlas_irq_type);
+               set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq);
 }
 
 static struct irqaction atlasirq = {

diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index d817c60c5ca50caeb08ff5390517083e707828a5..e4604c73f02e9dd75099e5c9a51af8d9fcd6d759 100644 (file)
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -288,6 +288,7 @@ void __init plat_timer_setup(struct irqaction *irq)
           The effect is that the int remains disabled on the second cpu.
           Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
        irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
+       set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 #endif
 
         /* to generate the first timer interrupt */

diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
index 24a4ed00cc0a0f39786a5e6749dadff0aee6296d..f2d998d2c169dc137084df7b5f469e4ded65be34 100644 (file)
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -203,7 +203,8 @@ void __init plat_timer_setup(struct irqaction *irq)
           on seperate cpu's the first one tries to handle the second interrupt.
           The effect is that the int remains disabled on the second cpu.
           Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
-       irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
+       irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
+       set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 #endif
 
        /* to generate the first timer interrupt */

diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index 7723f0998944b871f9c355e2e8708d421e3e3a11..e5a4a0a8a7f05821c6b03a11a2531fcb02663f6f 100644 (file)
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -106,5 +106,5 @@ void cpci_irq_init(void)
        int i;
 
        for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
-               set_irq_chip(i, &cpci_irq_type);
+               set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
 }

diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 72faf81b36ccc6835fd5ca246239f126e9c60b40..0029f0008deac076d76a5c9dcbf27704671b4aab 100644 (file)
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -96,6 +96,6 @@ struct irq_chip uart_irq_type = {
 
 void uart_irq_init(void)
 {
-       set_irq_chip(80, &uart_irq_type);
-       set_irq_chip(81, &uart_irq_type);
+       set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq);
+       set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq);
 }

diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index e4bf494dd43511a5dbe6319804a401c8aaac4ba7..0dc23930edbdf4fcdf0bd6ad81210534d1151e8c 100644 (file)
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -192,7 +192,7 @@ void __init arch_init_irq(void)
        int configPR;
 
        for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
-               set_irq_chip(i, &level_irq_type);
+               set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
                mask_irq(i);    /* mask the irq just in case  */
        }
 
@@ -229,7 +229,7 @@ void __init arch_init_irq(void)
                /* mask/priority is still 0 so we will not get any
                 * interrupts until it is unmasked */
 
-               set_irq_chip(i, &level_irq_type);
+               set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
        }
 
        /* Priority level 0 */
@@ -238,19 +238,21 @@ void __init arch_init_irq(void)
        /* Set int vector table address */
        PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
 
-       set_irq_chip(MIPS_CPU_GIC_IRQ, &level_irq_type);
+       set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
+                                handle_level_irq);
        setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
 
        /* init of Timer interrupts */
        for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
-               set_irq_chip(i, &level_irq_type);
+               set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
 
        /* Stop Timer 1-3 */
        configPR = read_c0_config7();
        configPR |= 0x00000038;
        write_c0_config7(configPR);
 
-       set_irq_chip(MIPS_CPU_TIMER_IRQ, &level_irq_type);
+       set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
+                                handle_level_irq);
        setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
 }
 

diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 8e2074b4ce43b4ca57524b702e936d62ca6543cd..c7b138053159f5d9f82ada27ac860f7404734445 100644 (file)
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -358,7 +358,7 @@ void __init arch_init_irq(void)
                else
                        handler         = &ip22_local3_irq_type;
 
-               set_irq_chip(i, handler);
+               set_irq_chip_and_handler(i, handler, handle_level_irq);
        }
 
        /* vector handler. this register the IRQ as non-sharable */

diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 824320281a3afb40b829967c8f5843fca80eea49..5f8835b4e84ad0fafaedcca7c1e3251062fa1a61 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -352,7 +352,7 @@ static struct irq_chip bridge_irq_type = {
 
 void __devinit register_bridge_irq(unsigned int irq)
 {
-       set_irq_chip(irq, &bridge_irq_type);
+       set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
 }
 
 int __devinit request_bridge_irq(struct bridge_controller *bc)

diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 86ba7fc10c3806c993d5291b9892b70ab1da6fc7..e5441c3a0b07d234c2889a1f33ccd89038178c17 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -190,6 +190,7 @@ static struct irq_chip rt_irq_type = {
        .mask           = disable_rt_irq,
        .mask_ack       = disable_rt_irq,
        .unmask         = enable_rt_irq,
+       .eoi            = enable_rt_irq,
        .end            = end_rt_irq,
 };
 
@@ -207,7 +208,7 @@ void __init plat_timer_setup(struct irqaction *irq)
        if (irqno < 0)
                panic("Can't allocate interrupt number for timer interrupt");
 
-       set_irq_chip(irqno, &rt_irq_type);
+       set_irq_chip_and_handler(irqno, &rt_irq_type, handle_percpu_irq);
 
        /* over-write the handler, we use our own way */
        irq->handler = no_action;

diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index 2c57ced5c68c14d19d9a63ff7b4d1b9879c58171..21873de49aa80425645ac9963cfd6dff1c0ff1fd 100644 (file)
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -196,7 +196,8 @@ static void __init tx4927_irq_cp0_init(void)
                           TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END);
 
        for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++)
-               set_irq_chip(i, &tx4927_irq_cp0_type);
+               set_irq_chip_and_handler(i, &tx4927_irq_cp0_type,
+                                        handle_level_irq);
 }
 
 static void tx4927_irq_cp0_enable(unsigned int irq)
@@ -350,7 +351,8 @@ static void __init tx4927_irq_pic_init(void)
                           TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END);
 
        for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++)
-               set_irq_chip(i, &tx4927_irq_pic_type);
+               set_irq_chip_and_handler(i, &tx4927_irq_pic_type,
+                                        handle_level_irq);
 
        setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
 

diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 1fdace89ae6d0d16db4de979e85a78a214c657df..34cdb2a240e991869fd0294fbb839be1ea5b240d 100644 (file)
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -342,7 +342,8 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
 
        for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
             i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
-               set_irq_chip(i, &toshiba_rbtx4927_irq_ioc_type);
+               set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
+                                        handle_level_irq);
 
        setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
                  &toshiba_rbtx4927_irq_ioc_action);

diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index 19c9ee9e3d0c539f8b6c261a9784ca2fb6313f32..42e127683ae961f0b18c17ef940b1e31e964c47f 100644 (file)
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -88,7 +88,8 @@ tx4938_irq_cp0_init(void)
        int i;
 
        for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++)
-               set_irq_chip(i, &tx4938_irq_cp0_type);
+               set_irq_chip_and_handler(i, &tx4938_irq_cp0_type,
+                                        handle_level_irq);
 }
 
 static void
@@ -245,7 +246,8 @@ tx4938_irq_pic_init(void)
        int i;
 
        for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++)
-               set_irq_chip(i, &tx4938_irq_pic_type);
+               set_irq_chip_and_handler(i, &tx4938_irq_pic_type,
+                                        handle_level_irq);
 
        setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
 

diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 2735ffe9ec284433e07b3df5d5d724038ffdbcf0..8c87a35f30682405abea6261152916000ec50d46 100644 (file)
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -136,7 +136,8 @@ toshiba_rbtx4938_irq_ioc_init(void)
 
        for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
             i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++)
-               set_irq_chip(i, &toshiba_rbtx4938_irq_ioc_type);
+               set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
+                                        handle_level_irq);
 
        setup_irq(RBTX4938_IRQ_IOCINT,
                  &toshiba_rbtx4938_irq_ioc_action);

diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index 33d70a6547adb54c662bbc3df761f70d863568bf..54b92a74c7ac2cad60c6a0985758208f7c5b671e 100644 (file)
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -701,10 +701,12 @@ static int __init vr41xx_icu_init(void)
        icu2_write(MGIUINTHREG, 0xffff);
 
        for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
-               set_irq_chip(i, &sysint1_irq_type);
+               set_irq_chip_and_handler(i, &sysint1_irq_type,
+                                        handle_level_irq);
 
        for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
-               set_irq_chip(i, &sysint2_irq_type);
+               set_irq_chip_and_handler(i, &sysint2_irq_type,
+                                        handle_level_irq);
 
        cascade_irq(INT0_IRQ, icu_get_irq);
        cascade_irq(INT1_IRQ, icu_get_irq);

diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 35a05ca5560cf75bf4d8cc865cc21231a08311cc..aed370770225793ff721a1c4d545f0f7a4e9f9a8 100644 (file)
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -57,7 +57,7 @@ do {                                                                  \
 do {                                                                   \
        irq_enter();                                                    \
        __DO_IRQ_SMTC_HOOK();                                           \
-       __do_IRQ((irq));                                                \
+       generic_handle_irq(irq);                                        \
        irq_exit();                                                     \
 } while (0)