OMAP: HSMMC: Fix suspend/resume for MMCHS2

For HSMMC2 and HSMMC3 set SDVSS to 1.8V in HCTL before enabling the SDBP bit.

Signed-off-by: Jarkko Lavinen <jarkko.lavinen@nokia.com>

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index a134f76ede2354c71c8bd6beb4907ca3aa47bdc7..4bc25c0d51dc4396a787b76b072a7a2786d879f3 100644 (file)
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1197,15 +1197,16 @@ static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
                        }
 
                        if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
-                               OMAP_HSMMC_WRITE(host->base, HCTL,
-                                       OMAP_HSMMC_READ(host->base, HCTL)
-                                       & SDVSCLR);
-                               OMAP_HSMMC_WRITE(host->base, HCTL,
-                                       OMAP_HSMMC_READ(host->base, HCTL)
-                                       | SDVS30);
-                               OMAP_HSMMC_WRITE(host->base, HCTL,
-                                       OMAP_HSMMC_READ(host->base, HCTL)
-                                       | SDBP);
+                               u32 hctl = OMAP_HSMMC_READ(host->base, HCTL) &
+                                       SDVSCLR;
+
+                               if (host->id == OMAP_MMC1_DEVID)
+                                       hctl |= SDVS30;
+                               else
+                                       hctl |= SDVS18;
+
+                               OMAP_HSMMC_WRITE(host->base, HCTL, hctl);
+                               OMAP_HSMMC_WRITE(host->base, HCTL, hctl | SDBP);
                        }
 
                        mmc_omap_fclk_state(host, OFF);