rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
 {
        struct phy_reg phy_reg_init[] = {
                { 0x1f, 0x0001 },
        mdio_write(ioaddr, 0x1f, 0x0000);
 }
 
-static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
 {
        struct phy_reg phy_reg_init[] = {
                { 0x1f, 0x0001 },
                rtl8168cp_hw_phy_config(ioaddr);
                break;
        case RTL_GIGA_MAC_VER_19:
-               rtl8168c_hw_phy_config(ioaddr);
+               rtl8168c_1_hw_phy_config(ioaddr);
                break;
        case RTL_GIGA_MAC_VER_20:
-               rtl8168cx_hw_phy_config(ioaddr);
+               rtl8168c_2_hw_phy_config(ioaddr);
                break;
        default:
                break;
        }
 }
 
+static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
+}
+
+static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       rtl_hw_start_8168bb(ioaddr, pdev);
+}
+
+static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
+}
+
+static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       __rtl_hw_start_8168cp(ioaddr, pdev);
+}
+
+static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       __rtl_hw_start_8168cp(ioaddr, pdev);
+}
+
+static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       __rtl_hw_start_8168cp(ioaddr, pdev);
+}
+
 static void rtl_hw_start_8168(struct net_device *dev)
 {
        struct rtl8169_private *tp = netdev_priv(dev);
 
        RTL_R8(IntrMask);
 
-       rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
+       switch (tp->mac_version) {
+       case RTL_GIGA_MAC_VER_11:
+               rtl_hw_start_8168bb(ioaddr, pdev);
+       break;
+
+       case RTL_GIGA_MAC_VER_12:
+       case RTL_GIGA_MAC_VER_17:
+               rtl_hw_start_8168bef(ioaddr, pdev);
+       break;
+
+       case RTL_GIGA_MAC_VER_18:
+               rtl_hw_start_8168cp(ioaddr, pdev);
+       break;
+
+       case RTL_GIGA_MAC_VER_19:
+               rtl_hw_start_8168c_1(ioaddr, pdev);
+       break;
+
+       case RTL_GIGA_MAC_VER_20:
+               rtl_hw_start_8168c_2(ioaddr, pdev);
+       break;
+
+       default:
+               printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
+                       dev->name, tp->mac_version);
+       break;
+       }
 
        RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);