};
 
 
+static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
+{
+       u32 crc_value;
+       crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad));
+
+       /*
+        * With commit ef19454b ("[LIB] crc32c: Keep intermediate crc
+        * state in cpu order"), behavior of crc32c changes on
+        * big-endian platforms.  Our algorithm expects the previous
+        * behavior; otherwise we have RDMA connection establishment
+        * issue on big-endian.
+        */
+       return cpu_to_le32(crc_value);
+}
+
 static inline void
 set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
 {
 
        struct iw_cm_event cm_event;
        struct nes_hw_qp_wqe *wqe;
        struct nes_v4_quad nes_quad;
+       u32 crc_value;
        int ret;
 
        ibqp = nes_get_qp(cm_id->device, conn_param->qpn);
        nes_quad.TcpPorts[1]   = cm_id->local_addr.sin_port;
 
        /* Produce hash key */
-       nesqp->hte_index = cpu_to_be32(
-                       crc32c(~0, (void *)&nes_quad, sizeof(nes_quad)) ^ 0xffffffff);
+       crc_value = get_crc_value(&nes_quad);
+       nesqp->hte_index = cpu_to_be32(crc_value ^ 0xffffffff);
        nes_debug(NES_DBG_CM, "HTE Index = 0x%08X, CRC = 0x%08X\n",
                        nesqp->hte_index, nesqp->hte_index & adapter->hte_index_mask);
 
        struct iw_cm_event cm_event;
        struct nes_hw_qp_wqe *wqe;
        struct nes_v4_quad nes_quad;
+       u32 crc_value;
        int ret;
 
        /* get all our handles */
        nes_quad.TcpPorts[1] = cm_id->local_addr.sin_port;
 
        /* Produce hash key */
-       nesqp->hte_index = cpu_to_be32(
-                       crc32c(~0, (void *)&nes_quad, sizeof(nes_quad)) ^ 0xffffffff);
+       crc_value = get_crc_value(&nes_quad);
+       nesqp->hte_index = cpu_to_be32(crc_value ^ 0xffffffff);
        nes_debug(NES_DBG_CM, "HTE Index = 0x%08X, After CRC = 0x%08X\n",
                        nesqp->hte_index, nesqp->hte_index & nesadapter->hte_index_mask);