return -ENODEV;
 }
 
+/* Determining link for parallel detection. */
 static int
 bnx2_5706_serdes_has_link(struct bnx2 *bp)
 {
        u32 mode_ctl, an_dbg, exp;
 
+       if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
+               return 0;
+
        bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
        bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
 
                        bp->flags |= BNX2_FLAG_NO_WOL;
                        bp->wol = 0;
                }
-               if (CHIP_NUM(bp) != CHIP_NUM_5706) {
+               if (CHIP_NUM(bp) == CHIP_NUM_5706) {
+                       /* Don't do parallel detect on this board because of
+                        * some board problems.  The link will not go down
+                        * if we do parallel detect.
+                        */
+                       if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
+                           pdev->subsystem_device == 0x310c)
+                               bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
+               } else {
                        bp->phy_addr = 2;
                        if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
                                bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
 
 #define BNX2_PHY_FLAG_DIS_EARLY_DAC            0x00000400
 #define BNX2_PHY_FLAG_REMOTE_PHY_CAP           0x00000800
 #define BNX2_PHY_FLAG_FORCED_DOWN              0x00001000
+#define BNX2_PHY_FLAG_NO_PARALLEL              0x00002000
 
        u32                     mii_bmcr;
        u32                     mii_bmsr;