struct cppi_descriptor *bdPtr;
struct musb_hw_ep *hw_ep = NULL;
- cppi = container_of(musb->pDmaController, struct cppi, Controller);
+ cppi = container_of(musb->dma_controller, struct cppi, Controller);
regBase = musb->ctrl_base;
ep->busy = 1;
if (is_dma_capable() && ep->dma) {
- struct dma_controller *c = ep->musb->pDmaController;
+ struct dma_controller *c = ep->musb->dma_controller;
int value;
if (ep->is_in) {
musb_writew(epio, MGC_O_HDRC_TXCSR,
#ifndef CONFIG_USB_INVENTRA_FIFO
if (is_dma_capable() && musb_ep->dma) {
- struct dma_controller *c = musb->pDmaController;
+ struct dma_controller *c = musb->dma_controller;
use_dma = (pRequest->dma != DMA_ADDR_INVALID);
musb_writew(epio, MGC_O_HDRC_TXCSR, wCsrVal);
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
- musb->pDmaController->channel_abort(dma);
+ musb->dma_controller->channel_abort(dma);
}
if (pRequest)
wCsrVal = musb_readw(epio, MGC_O_HDRC_RXCSR);
if (is_cppi_enabled() && musb_ep->dma) {
- struct dma_controller *c = musb->pDmaController;
+ struct dma_controller *c = musb->dma_controller;
struct dma_channel *channel = musb_ep->dma;
/* NOTE: CPPI won't actually stop advancing the DMA
struct dma_channel *channel;
int use_dma = 0;
- c = musb->pDmaController;
+ c = musb->dma_controller;
channel = musb_ep->dma;
/* We use DMA Req mode 0 in RxCsr, and DMA controller operates in
#ifdef CONFIG_USB_TUSB_OMAP_DMA
if (tusb_dma_omap() && musb_ep->dma) {
- struct dma_controller *c = musb->pDmaController;
+ struct dma_controller *c = musb->dma_controller;
struct dma_channel *channel = musb_ep->dma;
u32 dma_addr = pRequest->dma + pRequest->actual;
int ret;
if (wCsrVal & MGC_M_RXCSR_P_SENTSTALL) {
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
- (void) musb->pDmaController->channel_abort(dma);
+ (void) musb->dma_controller->channel_abort(dma);
pRequest->actual += musb_ep->dma->dwActualLength;
}
/* NOTE: all the I/O code _should_ work fine without DMA, in case
* for some reason you run out of channels here.
*/
- if (is_dma_capable() && musb->pDmaController) {
- struct dma_controller *c = musb->pDmaController;
+ if (is_dma_capable() && musb->dma_controller) {
+ struct dma_controller *c = musb->dma_controller;
musb_ep->dma = c->channel_alloc(c, hw_ep,
(desc->bEndpointAddress & USB_DIR_IN));
/* ... else abort the dma transfer ... */
else if (is_dma_capable() && musb_ep->dma) {
- struct dma_controller *c = musb->pDmaController;
+ struct dma_controller *c = musb->dma_controller;
musb_ep_select(musb->mregs, musb_ep->current_epnum);
if (c->channel_abort)
struct urb *pUrb, unsigned int is_out,
u8 * pBuffer, u32 dwLength)
{
- struct dma_controller *pDmaController;
+ struct dma_controller *dma_controller;
struct dma_channel *pDmaChannel;
u8 bDmaOk;
void __iomem *mbase = musb->mregs;
musb_ep_select(mbase, epnum);
/* candidate for DMA? */
- pDmaController = musb->pDmaController;
- if (is_dma_capable() && epnum && pDmaController) {
+ dma_controller = musb->dma_controller;
+ if (is_dma_capable() && epnum && dma_controller) {
pDmaChannel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
if (!pDmaChannel) {
- pDmaChannel = pDmaController->channel_alloc(
- pDmaController, hw_ep, is_out);
+ pDmaChannel = dma_controller->channel_alloc(
+ dma_controller, hw_ep, is_out);
if (is_out)
hw_ep->tx_channel = pDmaChannel;
else
musb_writew(epio, MGC_O_HDRC_TXCSR, wCsr);
- bDmaOk = pDmaController->channel_program(
+ bDmaOk = dma_controller->channel_program(
pDmaChannel, wPacketSize,
pDmaChannel->bDesiredMode,
pUrb->transfer_dma,
if (bDmaOk) {
wLoadCount = 0;
} else {
- pDmaController->channel_release(pDmaChannel);
+ dma_controller->channel_release(pDmaChannel);
if (is_out)
hw_ep->tx_channel = NULL;
else
/* TX uses "rndis" mode automatically, but needs help
* to identify the zero-length-final-packet case.
*/
- bDmaOk = pDmaController->channel_program(
+ bDmaOk = dma_controller->channel_program(
pDmaChannel, wPacketSize,
(pUrb->transfer_flags
& URB_ZERO_PACKET)
if (bDmaOk) {
wLoadCount = 0;
} else {
- pDmaController->channel_release(pDmaChannel);
+ dma_controller->channel_release(pDmaChannel);
pDmaChannel = hw_ep->tx_channel = NULL;
/* REVISIT there's an error path here that
/* unless caller treats short rx transfers as
* errors, we dare not queue multiple transfers.
*/
- bDmaOk = pDmaController->channel_program(
+ bDmaOk = dma_controller->channel_program(
pDmaChannel, wPacketSize,
!(pUrb->transfer_flags
& URB_SHORT_NOT_OK),
pUrb->transfer_dma,
qh->segsize);
if (!bDmaOk) {
- pDmaController->channel_release(
+ dma_controller->channel_release(
pDmaChannel);
pDmaChannel = hw_ep->rx_channel = NULL;
} else
if (status) {
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
- (void) musb->pDmaController->channel_abort(dma);
+ (void) musb->dma_controller->channel_abort(dma);
}
/* do the proper sequence to abort the transfer in the
/* clean up dma and collect transfer count */
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
- (void) musb->pDmaController->channel_abort(dma);
+ (void) musb->dma_controller->channel_abort(dma);
xfer_len = dma->dwActualLength;
}
musb_h_flush_rxfifo(hw_ep, 0);
*/
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
- (void) musb->pDmaController->channel_abort(dma);
+ (void) musb->dma_controller->channel_abort(dma);
xfer_len = dma->dwActualLength;
bDone = TRUE;
}
qh->offset,
pUrb->transfer_buffer_length);
- c = musb->pDmaController;
+ c = musb->dma_controller;
dma->bDesiredMode = 0;
#ifdef USE_MODE1
dma = is_in ? ep->rx_channel : ep->tx_channel;
if (dma) {
- status = ep->musb->pDmaController->channel_abort(dma);
+ status = ep->musb->dma_controller->channel_abort(dma);
DBG(status ? 1 : 3,
"abort %cX%d DMA for urb %p --> %d\n",
is_in ? 'R' : 'T', ep->epnum,
buffer += code;
#endif /* DAVINCI */
- if (is_cppi_enabled() && musb->pDmaController) {
+ if (is_cppi_enabled() && musb->dma_controller) {
code = sprintf(buffer,
"CPPI: txcr=%d txsrc=%01x txena=%01x; "
"rxcr=%d rxsrc=%01x rxena=%01x "
*/
void (*board_set_vbus)(struct musb *, int is_on);
- struct dma_controller *pDmaController;
+ struct dma_controller *dma_controller;
struct device *controller;
void __iomem *ctrl_base;
disable_irq_wake(musb->nIrq);
free_irq(musb->nIrq, musb);
}
- if (is_dma_capable() && musb->pDmaController) {
- struct dma_controller *c = musb->pDmaController;
+ if (is_dma_capable() && musb->dma_controller) {
+ struct dma_controller *c = musb->dma_controller;
(void) c->stop(c->pPrivateData);
dma_controller_destroy(c);
struct dma_controller *c;
c = dma_controller_create(musb, musb->mregs);
- musb->pDmaController = c;
+ musb->dma_controller = c;
if (c)
(void) c->start(c->pPrivateData);
}
#endif
/* ideally this would be abstracted in platform setup */
- if (!is_dma_capable() || !musb->pDmaController)
+ if (!is_dma_capable() || !musb->dma_controller)
dev->dma_mask = NULL;
/* be sure interrupts are disabled before connecting ISR */
default: s = "OTG"; break;
}; s; }),
ctrl,
- (is_dma_capable() && musb->pDmaController)
+ (is_dma_capable() && musb->dma_controller)
? "DMA" : "PIO",
musb->nIrq);