[P2] = R1;
        SSYNC;
 
-       p0.h = hi(SIC_IWR0);
-       p0.l = lo(SIC_IWR0);
-       r0.l = lo(IWR_ENABLE_ALL);
-       r0.h = hi(IWR_ENABLE_ALL);
-       [p0] = r0;
-       SSYNC;
-
        RTS;
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
 
        [P2] = R1;
        SSYNC;
 
-       p0.h = hi(SIC_IWR);
-       p0.l = lo(SIC_IWR);
-       r0.l = lo(IWR_ENABLE_ALL);
-       r0.h = hi(IWR_ENABLE_ALL);
-       [p0] = r0;
-       SSYNC;
-
        RTS;
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
 
        [P2] = R1;
        SSYNC;
 
-       p0.h = hi(SIC_IWR);
-       p0.l = lo(SIC_IWR);
-       r0.l = lo(IWR_ENABLE_ALL);
-       r0.h = hi(IWR_ENABLE_ALL);
-       [p0] = r0;
-       SSYNC;
-
        RTS;
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
 
        SSYNC;
 #endif
 
-       p0.h = hi(SIC_IWR0);
-       p0.l = lo(SIC_IWR0);
-       r0.l = lo(IWR_ENABLE_ALL);
-       r0.h = hi(IWR_ENABLE_ALL);
-       [p0] = r0;
-       SSYNC;
-
        RTS;
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
 
        jump .Lforever;
 ENDPROC(_hibernate_mode)
 
-ENTRY(_deep_sleep)
-       [--SP] = ( R7:0, P5:0 );
-       [--SP] =  RETS;
-
-       CLI R4;
-
-       R0 = IWR_ENABLE(0);
-       R1 = IWR_DISABLE_ALL;
-       R2 = IWR_DISABLE_ALL;
-
-       call _set_sic_iwr;
-
-       call _set_dram_srfs;
-
-       /* Clear all the interrupts,bits sticky */
-       R0 = 0xFFFF (Z);
-       call _set_rtc_istat
-
-       P0.H = hi(PLL_CTL);
-       P0.L = lo(PLL_CTL);
-       R0 = W[P0](z);
-       BITSET (R0, 5);
-       W[P0] = R0.L;
-
-       call _test_pll_locked;
-
-       SSYNC;
-       IDLE;
-
-       call _unset_dram_srfs;
-
-       call _test_pll_locked;
-
-       R0 = IWR_ENABLE(0);
-       R1 = IWR_DISABLE_ALL;
-       R2 = IWR_DISABLE_ALL;
-
-       call _set_sic_iwr;
-
-       P0.H = hi(PLL_CTL);
-       P0.L = lo(PLL_CTL);
-       R0 = w[p0](z);
-       BITCLR (R0, 3);
-       BITCLR (R0, 5);
-       BITCLR (R0, 8);
-       w[p0] = R0;
-       IDLE;
-       call _test_pll_locked;
-
-       STI R4;
-
-       RETS = [SP++];
-       ( R7:0, P5:0 ) = [SP++];
-       RTS;
-ENDPROC(_deep_sleep)
-
 ENTRY(_sleep_deeper)
        [--SP] = ( R7:0, P5:0 );
        [--SP] =  RETS;
 
            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 
 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
-       bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
-       bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
+       bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
+       bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
 # ifdef CONFIG_BF54x
-       bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
+       bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
 # endif
 #else
-       bfin_write_SIC_IWR(IWR_ENABLE_ALL);
+       bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
 
        return 0;
 
        bfin_pm_standby_restore();
 
 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
-       bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
-       bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
+       bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
+       bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
 # ifdef CONFIG_BF54x
-       bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
+       bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
 # endif
 #else
-       bfin_write_SIC_IWR(IWR_ENABLE_ALL);
+       bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
 
        local_irq_restore(flags);
 
 #ifndef __ASSEMBLY__
 
 void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void do_hibernate(int wakeup);