Commit 
2ccdd1e77da52ad494e9af46bf272d816830cb28 doesn't add
v7wbi_possible_flags and v7wbi_always_flags to possible_tlb_flags and
always_tlb_flags.  This causes the L2 cache flush in clean_pmd_entry()
(intended for Feroceon only) to execute on ARMv7, and the CPU hangs.
This patch is required for OMAP3 boards to boot.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Acked-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
  *       v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
  *       fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
  *       v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
+ *       v7wbi - identical to v6wbi
  */
 #undef _TLB
 #undef MULTI_TLB
                                 v4wbi_possible_flags | \
                                 fr_possible_flags | \
                                 v4wb_possible_flags | \
-                                v6wbi_possible_flags)
+                                v6wbi_possible_flags | \
+                                v7wbi_possible_flags)
 
 #define always_tlb_flags       (v3_always_flags & \
                                 v4_always_flags & \
                                 v4wbi_always_flags & \
                                 fr_always_flags & \
                                 v4wb_always_flags & \
-                                v6wbi_always_flags)
+                                v6wbi_always_flags & \
+                                v7wbi_always_flags)
 
 #define tlb_flag(f)    ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))