return 0;
 }
 
+#ifdef CONFIG_PM
+
+static u32 wakeups;
+static u32 backups;
+
+static int at91rm9200_irq_set_wake(unsigned irq, unsigned value)
+{
+       if (unlikely(irq >= 32))
+               return -EINVAL;
+
+       if (value)
+               wakeups |= (1 << irq);
+       else
+               wakeups &= ~(1 << irq);
+
+       return 0;
+}
+
+void at91_irq_suspend(void)
+{
+       backups = at91_sys_read(AT91_AIC_IMR);
+       at91_sys_write(AT91_AIC_IDCR, backups);
+       at91_sys_write(AT91_AIC_IECR, wakeups);
+}
+
+void at91_irq_resume(void)
+{
+       at91_sys_write(AT91_AIC_IDCR, wakeups);
+       at91_sys_write(AT91_AIC_IECR, backups);
+}
+
+#else
+#define at91rm9200_irq_set_wake        NULL
+#endif
+
 static struct irqchip at91rm9200_irq_chip = {
        .ack            = at91rm9200_mask_irq,
        .mask           = at91rm9200_mask_irq,
        .unmask         = at91rm9200_unmask_irq,
        .set_type       = at91rm9200_irq_type,
+       .set_wake       = at91rm9200_irq_set_wake,
 };
 
 /*