[SPARC]: Add reboot_command[] extern decl to asm/system.h

Kill off some sparse warnings.

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/sparc/kernel/process.c b/arch/sparc/kernel/process.c
index 0bd69d0b5cd7f75ee293d06ff4ab3c81a0ec48dd..70c0dd22491d2a5e4d3e4aaf1ebdc72ec7ca855f 100644 (file)
--- a/arch/sparc/kernel/process.c
+++ b/arch/sparc/kernel/process.c
@@ -139,8 +139,6 @@ void cpu_idle(void)
 
 #endif
 
-extern char reboot_command [];
-
 /* XXX cli/sti -> local_irq_xxx here, check this works once SMP is fixed. */
 void machine_halt(void)
 {

diff --git a/arch/sparc64/kernel/process.c b/arch/sparc64/kernel/process.c
index 2aafce7dfc0ecf31b42ba94f422032208553220e..e116e38b160ec3cd9a9b8a5aaecfef2ff2d659db 100644 (file)
--- a/arch/sparc64/kernel/process.c
+++ b/arch/sparc64/kernel/process.c
@@ -114,8 +114,6 @@ void cpu_idle(void)
        }
 }
 
-extern char reboot_command [];
-
 void machine_halt(void)
 {
        sstate_halt();

diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h
index 45e47c159a6e55316e74a35cdd2303b8fb0586a0..4e08210cd4c2a33b22eceb46c1788071deae9cdc 100644 (file)
--- a/include/asm-sparc/system.h
+++ b/include/asm-sparc/system.h
@@ -44,6 +44,8 @@ extern enum sparc_cpu sparc_cpu_model;
 
 #define SUN4M_NCPUS            4              /* Architectural limit of sun4m. */
 
+extern char reboot_command[];
+
 extern struct thread_info *current_set[NR_CPUS];
 
 extern unsigned long empty_bad_page;

diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index ed91a5d8d4f05dce3c5ebe2f54d5e3f0ce510907..53eae091a171920d90dbc083d5fb96d0a8f67b3e 100644 (file)
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -30,6 +30,8 @@ enum sparc_cpu {
 #define ARCH_SUN4C_SUN4 0
 #define ARCH_SUN4 0
 
+extern char reboot_command[];
+
 /* These are here in an effort to more fully work around Spitfire Errata
  * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
  * branch, the chip can stop executing instructions until a trap occurs.