ultra_timing    &= ~(0x0F << (4*unit));
        ultra_enable    &= ~(0x01 << drive->dn);
 
-       switch(speed) {
-               case XFER_MW_DMA_2:
-               case XFER_MW_DMA_1:
-               case XFER_MW_DMA_0:
-                       dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
-                       break;
-
-               case XFER_UDMA_5:
-               case XFER_UDMA_4:
-               case XFER_UDMA_3:
-               case XFER_UDMA_2:
-               case XFER_UDMA_1:
-               case XFER_UDMA_0:
-                       dma_timing   |= dma_modes[2];
-                       ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
-                       ultra_enable |= (0x01 << drive->dn);
-               default:
-                       break;
-       }
+       if (speed >= XFER_UDMA_0) {
+               dma_timing   |= dma_modes[2];
+               ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
+               ultra_enable |= (0x01 << drive->dn);
+       } else if (speed >= XFER_MW_DMA_0)
+               dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];
 
        pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
        pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);