flash->mtd.erasesize = info->sector_size;
        }
 
+       flash->mtd.dev.parent = &spi->dev;
+
        dev_info(&spi->dev, "%s (%lld Kbytes)\n", info->name,
                        (long long)flash->mtd.size >> 10);
 
 
        device->write = dataflash_write;
        device->priv = priv;
 
+       device->dev.parent = &spi->dev;
+
        if (revision >= 'c')
                otp_tag = otp_setup(device, revision);
 
 
        }
        info->mtd->owner = THIS_MODULE;
 
+       info->mtd->dev.parent = &pdev->dev;
+
 #ifdef CONFIG_MTD_PARTITIONS
        err = parse_mtd_partitions(info->mtd, part_probes, &info->parts, 0);
        if (err > 0)
 
                        devices_found++;
                }
                info->mtd[i]->owner = THIS_MODULE;
+               info->mtd[i]->dev.parent = &dev->dev;
        }
 
        if (devices_found == 1) {
 
        }
 
        info->mtd->owner = THIS_MODULE;
+       info->mtd->dev.parent = &pdev->dev;
 
        platram_setrw(info, PLATRAM_RW);
 
 
        info->mtd.name          = dev_name(&pdev->dev);
        info->mtd.owner         = THIS_MODULE;
 
+       info->mtd.dev.parent    = &pdev->dev;
+
        info->chip.IO_ADDR_R    = vaddr;
        info->chip.IO_ADDR_W    = vaddr;
        info->chip.chip_delay   = 0;
 
        mtd = &host->mtd;
        mtd->priv = this;
        mtd->owner = THIS_MODULE;
+       mtd->dev.parent = &pdev->dev;
 
        /* 50 us command delay time */
        this->chip_delay = 5;
 
        c->mtd.priv = &c->onenand;
        c->mtd.owner = THIS_MODULE;
 
+       c->mtd.dev.parent = &pdev->dev;
+
        if (c->dma_channel >= 0) {
                struct onenand_chip *this = &c->onenand;