OMAP3 clock: put DPLL into bypass if bypass rate = clk->rate, not hardware rate

When a non-CORE DPLL is enabled via omap3_noncore_dpll_enable(), use
the user's desired rate in clk->rate to determine whether to put the
DPLL into bypass or lock mode, rather than reading the DPLL's current
idle state from its hardware registers.

This fixes a bug observed when leaving retention. Non-CORE DPLLs were
not being relocked when downstream clocks re-enabled; rather, the DPLL
entered bypass mode.

Problem reported by Tero Kristo <tero.kristo@nokia.com>.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index c89d6bcb197ca3069775b7704f233eaab2bb0c83..df258f762031bba6971e3eb9e7916dc2cd4a7913 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -281,9 +281,7 @@ static int omap3_noncore_dpll_enable(struct clk *clk)
        if (!dd)
                return -EINVAL;
 
-       rate = omap2_get_dpll_rate(clk);
-
-       if (dd->bypass_clk->rate == rate)
+       if (clk->rate == dd->bypass_clk->rate)
                r = _omap3_noncore_dpll_bypass(clk);
        else
                r = _omap3_noncore_dpll_lock(clk);