]> pilppa.org Git - linux-2.6-omap-h63xx.git/commitdiff
Detect the 34K.
authorRalf Baechle <ralf@linux-mips.org>
Tue, 12 Jul 2005 16:12:05 +0000 (16:12 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 29 Oct 2005 18:31:45 +0000 (19:31 +0100)
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/cpu-probe.c
arch/mips/kernel/proc.c
arch/mips/mm/tlbex.c
include/asm-mips/cpu.h

index 2b6db681417d11d108281a3ee105ffde4df440e7..e40bd6fccea588988edb829f0559950bb42d4055 100644 (file)
@@ -104,6 +104,7 @@ static inline void check_wait(void)
 /*     case CPU_20KC:*/
        case CPU_24K:
        case CPU_25KF:
+       case CPU_34K:
                cpu_wait = r4k_wait;
                printk(" available.\n");
                break;
@@ -538,6 +539,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
                /* Probe for L2 cache */
                c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
                break;
+       case PRID_IMP_34K:
+               c->cputype = CPU_34K;
+               c->isa_level = MIPS_CPU_ISA_M32;
+               break;
        }
 }
 
index cf31d3952d656bbcc57b4e10a16b063491bbf75b..1bd40af508ed45dd5a80a275c0f0ebcc2850856d 100644 (file)
@@ -72,6 +72,7 @@ static const char *cpu_name[] = {
        [CPU_20KC]      = "MIPS 20Kc",
        [CPU_24K]       = "MIPS 24K",
        [CPU_25KF]      = "MIPS 25Kf",
+       [CPU_34K]       = "MIPS 34K",
        [CPU_VR4111]    = "NEC VR4111",
        [CPU_VR4121]    = "NEC VR4121",
        [CPU_VR4122]    = "NEC VR4122",
index 7bd8584fafb2ad0de18c7bdc45748af59a67d613..c1d394d36f6cf946e7c900417d9b5a2f13505238 100644 (file)
@@ -879,6 +879,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
 
        case CPU_4KEC:
        case CPU_24K:
+       case CPU_34K:
                i_ehb(p);
                tlbw(p);
                break;
index 2a109a5e0932a449b5f7a3bd1fab103c6ea791c7..e6927442f7b4061eafcd08bbd4cfffea0b3bf022 100644 (file)
@@ -77,6 +77,7 @@
 #define PRID_IMP_4KEMPR2       0x9100
 #define PRID_IMP_4KSD          0x9200
 #define PRID_IMP_24K           0x9300
+#define PRID_IMP_34K           0x9500
 #define PRID_IMP_24KE          0x9600
 
 #define PRID_IMP_UNKNOWN       0xff00
 #define CPU_AU1550             57
 #define CPU_24K                        58
 #define CPU_AU1200             59
-#define CPU_LAST               59
+#define CPU_34K                        60
+#define CPU_LAST               60
 
 /*
  * ISA Level encodings