/* CM_FCLKEN_DSS */
 #define OMAP3430_EN_TV                                 (1 << 2)
-#define OMAP3430_EN_TV_SHIFT                                  2
+#define OMAP3430_EN_TV_SHIFT                           2
 #define OMAP3430_EN_DSS2                               (1 << 1)
 #define OMAP3430_EN_DSS2_SHIFT                         1
 #define OMAP3430_EN_DSS1                               (1 << 0)
 
 #define CM_ICLKEN2                                     0x0014
 #define CM_ICLKEN3                                     0x0018
 #define CM_IDLEST1                                     0x0020
-#define CM_IDLEST                                       CM_IDLEST1
+#define CM_IDLEST                                      CM_IDLEST1
 #define CM_IDLEST2                                     0x0024
 #define CM_AUTOIDLE                                    0x0030
 #define CM_AUTOIDLE1                                   0x0030
 /* Clock management domain register get/set */
 
 #ifndef __ASSEMBLER__
-static void __attribute__((unused)) cm_write_mod_reg(u32 val, s16 module, s16 idx)
+static void __attribute__((unused)) cm_write_mod_reg(u32 val, s16 module,
+                                                       s16 idx)
 {
        cm_write_reg(val, OMAP_CM_REGADDR(module, idx));
 }
 
 
 static u32 omap2_ctrl_base;
 
-#define OMAP_CTRL_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_ctrl_base + reg)
+#define OMAP_CTRL_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_ctrl_base \
+                                                               + (reg))
 
 void omap_ctrl_base_set(u32 base)
 {