s->sg_processed, s->sg_processing_size, itv->dma_retries);
                        write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
                        if (itv->dma_retries == 3) {
+                               /* Too many retries, give up on this frame */
                                itv->dma_retries = 0;
+                               s->sg_processed = s->sg_processing_size;
                        }
                        else {
                                /* Retry, starting with the first xfer segment.
                        s->dma_offset, s->sg_processed, s->sg_processing_size, itv->dma_retries);
                write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
                if (itv->dma_retries == 3) {
+                       /* Too many retries, give up on this frame */
                        itv->dma_retries = 0;
+                       s->sg_processed = s->sg_processing_size;
                }
                else {
                        /* Retry, starting with the first xfer segment.
 
 
        /* Set the following Interrupt mask bits for capture */
        ivtv_set_irq_mask(itv, IVTV_IRQ_MASK_CAPTURE);
+       del_timer(&itv->dma_timer);
 
        /* event notification (off) */
        if (test_and_clear_bit(IVTV_F_I_DIG_RST, &itv->i_flags)) {
        ivtv_vapi(itv, CX2341X_DEC_SET_EVENT_NOTIFICATION, 4, 0, 0, IVTV_IRQ_DEC_AUD_MODE_CHG, -1);
 
        ivtv_set_irq_mask(itv, IVTV_IRQ_MASK_DECODE);
+       del_timer(&itv->dma_timer);
 
        clear_bit(IVTV_F_S_NEEDS_DATA, &s->s_flags);
        clear_bit(IVTV_F_S_STREAMING, &s->s_flags);