2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #if defined(CONFIG_DEBUG_ICEDCC)
26 mcr p14, 0, \ch, c0, c1, 0
30 #include <asm/arch/debug-macro.S>
36 #if defined(CONFIG_ARCH_SA1100)
38 mov \rb, #0x80000000 @ physical base address
39 #ifdef CONFIG_DEBUG_LL_SER3
40 add \rb, \rb, #0x00050000 @ Ser3
42 add \rb, \rb, #0x00010000 @ Ser1
45 #elif defined(CONFIG_ARCH_S3C2410)
48 add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
69 .macro debug_reloc_start
72 kphex r6, 8 /* processor id */
74 kphex r7, 8 /* architecture id */
76 mrc p15, 0, r0, c1, c0
77 kphex r0, 8 /* control reg */
79 kphex r5, 8 /* decompressed kernel start */
81 kphex r9, 8 /* decompressed kernel end */
83 kphex r4, 8 /* kernel execution address */
88 .macro debug_reloc_end
90 kphex r5, 8 /* end of kernel */
93 bl memdump /* dump 256 bytes at start of kernel */
97 .section ".start", #alloc, #execinstr
99 * sort out different calling conventions
103 .type start,#function
109 .word 0x016f2818 @ Magic numbers to help the loader
110 .word start @ absolute load/run zImage address
111 .word _edata @ zImage end address
112 1: mov r7, r1 @ save architecture ID
113 mov r8, r2 @ save atags pointer
115 #ifndef __ARM_ARCH_2__
117 * Booting from Angel - need to enter SVC mode and disable
118 * FIQs/IRQs (numeric definitions from angel arm.h source).
119 * We only do this if we were in user mode on entry.
121 mrs r2, cpsr @ get current mode
122 tst r2, #3 @ not user?
124 mov r0, #0x17 @ angel_SWIreason_EnterSVC
125 swi 0x123456 @ angel_SWI_ARM
127 mrs r2, cpsr @ turn off interrupts to
128 orr r2, r2, #0xc0 @ prevent angel from running
131 teqp pc, #0x0c000003 @ turn off interrupts
135 * Note that some cache flushing and other stuff may
136 * be needed here - is there an Angel SWI call for this?
140 * some architecture specific code can be inserted
141 * by the linker here, but it should preserve r7, r8, and r9.
146 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
147 subs r0, r0, r1 @ calculate the delta offset
149 @ if delta is zero, we are
150 beq not_relocated @ running at the address we
154 * We're running at a different address. We need to fix
155 * up various pointers:
156 * r5 - zImage base address
164 #ifndef CONFIG_ZBOOT_ROM
166 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
167 * we need to fix up pointers into the BSS region.
177 * Relocate all entries in the GOT table.
179 1: ldr r1, [r6, #0] @ relocate entries in the GOT
180 add r1, r1, r0 @ table. This fixes up the
181 str r1, [r6], #4 @ C references.
187 * Relocate entries in the GOT table. We only relocate
188 * the entries that are outside the (relocated) BSS region.
190 1: ldr r1, [r6, #0] @ relocate entries in the GOT
191 cmp r1, r2 @ entry < bss_start ||
192 cmphs r3, r1 @ _end < entry
193 addlo r1, r1, r0 @ table. This fixes up the
194 str r1, [r6], #4 @ C references.
199 not_relocated: mov r0, #0
200 1: str r0, [r2], #4 @ clear bss
208 * The C runtime environment should now be setup
209 * sufficiently. Turn the cache on, set up some
210 * pointers, and start decompressing.
214 mov r1, sp @ malloc space above stack
215 add r2, sp, #0x10000 @ 64k max
218 * Check to see if we will overwrite ourselves.
219 * r4 = final kernel address
220 * r5 = start of this image
221 * r2 = end of malloc space (and therefore this image)
224 * r4 + image length <= r5 -> OK
228 add r0, r4, #4096*1024 @ 4MB largest kernel size
232 mov r5, r2 @ decompress after malloc space
238 bic r0, r0, #127 @ align the kernel length
240 * r0 = decompressed kernel length
242 * r4 = kernel execution address
243 * r5 = decompressed kernel start
245 * r7 = architecture ID
249 add r1, r5, r0 @ end of decompressed kernel
253 1: ldmia r2!, {r9 - r14} @ copy relocation code
254 stmia r1!, {r9 - r14}
255 ldmia r2!, {r9 - r14}
256 stmia r1!, {r9 - r14}
261 add pc, r5, r0 @ call relocation code
264 * We're not in danger of overwriting ourselves. Do this the simple way.
266 * r4 = kernel execution address
267 * r7 = architecture ID
269 wont_overwrite: mov r0, r4
276 .word __bss_start @ r2
280 .word _got_start @ r6
282 .word user_stack+4096 @ sp
283 LC1: .word reloc_end - reloc_start
286 #ifdef CONFIG_ARCH_RPC
288 params: ldr r0, =params_phys
295 * Turn on the cache. We need to setup some page tables so that we
296 * can have both the I and D caches on.
298 * We place the page tables 16k down from the kernel execution address,
299 * and we hope that nothing else is using it. If we're using it, we
303 * r4 = kernel execution address
305 * r7 = architecture number
307 * r9 = run-time address of "start" (???)
309 * r1, r2, r3, r9, r10, r12 corrupted
310 * This routine must preserve:
314 cache_on: mov r3, #8 @ cache_on function
318 * Initialize the highest priority protection region, PR7
319 * to cover all 32bit address and cacheable and bufferable.
321 __armv4_mpu_cache_on:
322 mov r0, #0x3f @ 4G, the whole
323 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
324 mcr p15, 0, r0, c6, c7, 1
327 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
328 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
329 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
332 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
333 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
336 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
337 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
338 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
339 mrc p15, 0, r0, c1, c0, 0 @ read control reg
340 @ ...I .... ..D. WC.M
341 orr r0, r0, #0x002d @ .... .... ..1. 11.1
342 orr r0, r0, #0x1000 @ ...1 .... .... ....
344 mcr p15, 0, r0, c1, c0, 0 @ write control reg
347 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
348 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
351 __armv3_mpu_cache_on:
352 mov r0, #0x3f @ 4G, the whole
353 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
356 mcr p15, 0, r0, c2, c0, 0 @ cache on
357 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
360 mcr p15, 0, r0, c5, c0, 0 @ access permission
363 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
364 mrc p15, 0, r0, c1, c0, 0 @ read control reg
365 @ .... .... .... WC.M
366 orr r0, r0, #0x000d @ .... .... .... 11.1
368 mcr p15, 0, r0, c1, c0, 0 @ write control reg
370 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
373 __setup_mmu: sub r3, r4, #16384 @ Page directory size
374 bic r3, r3, #0xff @ Align the pointer
377 * Initialise the page tables, turning on the cacheable and bufferable
378 * bits for the RAM area only.
382 mov r9, r9, lsl #18 @ start of RAM
383 add r10, r9, #0x10000000 @ a reasonable RAM size
387 1: cmp r1, r9 @ if virt > start of RAM
388 orrhs r1, r1, #0x0c @ set cacheable, bufferable
389 cmp r1, r10 @ if virt > end of RAM
390 bichs r1, r1, #0x0c @ clear cacheable, bufferable
391 str r1, [r0], #4 @ 1:1 mapping
396 * If ever we are running from Flash, then we surely want the cache
397 * to be enabled also for our execution instance... We map 2MB of it
398 * so there is no map overlap problem for up to 1 MB compressed kernel.
399 * If the execution is in RAM then we would only be duplicating the above.
404 orr r1, r1, r2, lsl #20
405 add r0, r3, r2, lsl #2
411 __armv4_mmu_cache_on:
415 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
416 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
417 mrc p15, 0, r0, c1, c0, 0 @ read control reg
418 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
420 bl __common_mmu_cache_on
422 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
429 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
430 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
432 bl __common_mmu_cache_on
434 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
437 __common_mmu_cache_on:
439 orr r0, r0, #0x000d @ Write buffer, mmu
442 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
443 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
445 .align 5 @ cache line aligned
446 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
447 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
448 sub pc, lr, r0, lsr #32 @ properly flush pipeline
451 * All code following this line is relocatable. It is relocated by
452 * the above code to the end of the decompressed kernel image and
453 * executed there. During this time, we have no stacks.
455 * r0 = decompressed kernel length
457 * r4 = kernel execution address
458 * r5 = decompressed kernel start
460 * r7 = architecture ID
465 reloc_start: add r9, r5, r0
470 ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel
471 stmia r1!, {r0, r2, r3, r10 - r14}
478 call_kernel: bl cache_clean_flush
480 mov r0, #0 @ must be zero
481 mov r1, r7 @ restore architecture number
482 mov r2, r8 @ restore atags pointer
483 mov pc, r4 @ call kernel
486 * Here follow the relocatable cache support functions for the
487 * various processors. This is a generic hook for locating an
488 * entry and jumping to an instruction at the specified offset
489 * from the start of the block. Please note this is all position
499 call_cache_fn: adr r12, proc_types
500 mrc p15, 0, r6, c0, c0 @ get processor ID
501 1: ldr r1, [r12, #0] @ get value
502 ldr r2, [r12, #4] @ get mask
503 eor r1, r1, r6 @ (real ^ match)
505 addeq pc, r12, r3 @ call cache function
510 * Table for cache operations. This is basically:
513 * - 'cache on' method instruction
514 * - 'cache off' method instruction
515 * - 'cache flush' method instruction
517 * We match an entry using: ((real_id ^ match) & mask) == 0
519 * Writethrough caches generally only need 'on' and 'off'
520 * methods. Writeback caches _must_ have the flush method
523 .type proc_types,#object
525 .word 0x41560600 @ ARM6/610
527 b __arm6_mmu_cache_off @ works, but slow
528 b __arm6_mmu_cache_off
530 @ b __arm6_mmu_cache_on @ untested
531 @ b __arm6_mmu_cache_off
532 @ b __armv3_mmu_cache_flush
534 .word 0x00000000 @ old ARM ID
540 .word 0x41007000 @ ARM7/710
542 b __arm7_mmu_cache_off
543 b __arm7_mmu_cache_off
546 .word 0x41807200 @ ARM720T (writethrough)
548 b __armv4_mmu_cache_on
549 b __armv4_mmu_cache_off
552 .word 0x41007400 @ ARM74x
554 b __armv3_mpu_cache_on
555 b __armv3_mpu_cache_off
556 b __armv3_mpu_cache_flush
558 .word 0x41009400 @ ARM94x
560 b __armv4_mpu_cache_on
561 b __armv4_mpu_cache_off
562 b __armv4_mpu_cache_flush
564 .word 0x00007000 @ ARM7 IDs
570 @ Everything from here on will be the new ID system.
572 .word 0x4401a100 @ sa110 / sa1100
574 b __armv4_mmu_cache_on
575 b __armv4_mmu_cache_off
576 b __armv4_mmu_cache_flush
578 .word 0x6901b110 @ sa1110
580 b __armv4_mmu_cache_on
581 b __armv4_mmu_cache_off
582 b __armv4_mmu_cache_flush
584 @ These match on the architecture ID
586 .word 0x00020000 @ ARMv4T
588 b __armv4_mmu_cache_on
589 b __armv4_mmu_cache_off
590 b __armv4_mmu_cache_flush
592 .word 0x00050000 @ ARMv5TE
594 b __armv4_mmu_cache_on
595 b __armv4_mmu_cache_off
596 b __armv4_mmu_cache_flush
598 .word 0x00060000 @ ARMv5TEJ
600 b __armv4_mmu_cache_on
601 b __armv4_mmu_cache_off
602 b __armv4_mmu_cache_flush
604 .word 0x0007b000 @ ARMv6
606 b __armv4_mmu_cache_on
607 b __armv4_mmu_cache_off
608 b __armv6_mmu_cache_flush
610 .word 0 @ unrecognised type
616 .size proc_types, . - proc_types
619 * Turn off the Cache and MMU. ARMv3 does not support
620 * reading the control register, but ARMv4 does.
622 * On entry, r6 = processor ID
623 * On exit, r0, r1, r2, r3, r12 corrupted
624 * This routine must preserve: r4, r6, r7
627 cache_off: mov r3, #12 @ cache_off function
630 __armv4_mpu_cache_off:
631 mrc p15, 0, r0, c1, c0
633 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
635 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
636 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
637 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
640 __armv3_mpu_cache_off:
641 mrc p15, 0, r0, c1, c0
643 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
645 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
648 __armv4_mmu_cache_off:
649 mrc p15, 0, r0, c1, c0
651 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
653 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
654 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
657 __arm6_mmu_cache_off:
658 mov r0, #0x00000030 @ ARM6 control reg.
659 b __armv3_mmu_cache_off
661 __arm7_mmu_cache_off:
662 mov r0, #0x00000070 @ ARM7 control reg.
663 b __armv3_mmu_cache_off
665 __armv3_mmu_cache_off:
666 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
668 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
669 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
673 * Clean and flush the cache to maintain consistency.
678 * r1, r2, r3, r11, r12 corrupted
679 * This routine must preserve:
687 __armv4_mpu_cache_flush:
690 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
691 mov r1, #7 << 5 @ 8 segments
692 1: orr r3, r1, #63 << 26 @ 64 entries
693 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
694 subs r3, r3, #1 << 26
695 bcs 2b @ entries 63 to 0
697 bcs 1b @ segments 7 to 0
700 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
701 mcr p15, 0, ip, c7, c10, 4 @ drain WB
705 __armv6_mmu_cache_flush:
707 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
708 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
709 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
710 mcr p15, 0, r1, c7, c10, 4 @ drain WB
713 __armv4_mmu_cache_flush:
714 mov r2, #64*1024 @ default: 32K dcache size (*2)
715 mov r11, #32 @ default: 32 byte line size
716 mrc p15, 0, r3, c0, c0, 1 @ read cache type
717 teq r3, r6 @ cache ID register present?
722 mov r2, r2, lsl r1 @ base dcache size *2
723 tst r3, #1 << 14 @ test M bit
724 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
728 mov r11, r11, lsl r3 @ cache line size in bytes
730 bic r1, pc, #63 @ align to longest cache line
732 1: ldr r3, [r1], r11 @ s/w flush D cache
736 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
737 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
738 mcr p15, 0, r1, c7, c10, 4 @ drain WB
741 __armv3_mmu_cache_flush:
742 __armv3_mpu_cache_flush:
744 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
748 * Various debugging routines for printing hex characters and
749 * memory, which again must be relocatable.
752 .type phexbuf,#object
754 .size phexbuf, . - phexbuf
756 phex: adr r3, phexbuf
793 2: mov r0, r11, lsl #2
801 ldr r0, [r12, r11, lsl #2]
822 .section ".stack", "w"
823 user_stack: .space 4096