2 * linux/arch/arm/mach-iop33x/irq.c
4 * Generic IOP331 IRQ handling functionality
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003 Intel Corp.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
19 #include <asm/mach/irq.h>
21 #include <asm/hardware.h>
23 #include <asm/mach-types.h>
25 static u32 iop331_mask0 = 0;
26 static u32 iop331_mask1 = 0;
28 static inline void intctl_write0(u32 val)
32 asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
36 static inline void intctl_write1(u32 val)
40 asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
44 static inline void intstr_write0(u32 val)
48 asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
52 static inline void intstr_write1(u32 val)
56 asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
60 static inline void intbase_write(u32 val)
63 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
67 static inline void intsize_write(u32 val)
70 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
75 iop331_irq_mask1 (unsigned int irq)
77 iop331_mask0 &= ~(1 << irq);
78 intctl_write0(iop331_mask0);
82 iop331_irq_mask2 (unsigned int irq)
84 iop331_mask1 &= ~(1 << (irq - 32));
85 intctl_write1(iop331_mask1);
89 iop331_irq_unmask1(unsigned int irq)
91 iop331_mask0 |= (1 << irq);
92 intctl_write0(iop331_mask0);
96 iop331_irq_unmask2(unsigned int irq)
98 iop331_mask1 |= (1 << (irq - 32));
99 intctl_write1(iop331_mask1);
102 struct irq_chip iop331_irqchip1 = {
104 .ack = iop331_irq_mask1,
105 .mask = iop331_irq_mask1,
106 .unmask = iop331_irq_unmask1,
109 struct irq_chip iop331_irqchip2 = {
111 .ack = iop331_irq_mask2,
112 .mask = iop331_irq_mask2,
113 .unmask = iop331_irq_unmask2,
116 void __init iop331_init_irq(void)
120 intctl_write0(0); // disable all interrupts
122 intstr_write0(0); // treat all as IRQ
126 if(machine_is_iq80331()) // all interrupts are inputs to chip
127 *IOP3XX_PCIIRSR = 0x0f;
129 for(i = 0; i < NR_IRQS; i++)
131 set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
132 set_irq_handler(i, do_level_IRQ);
133 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);