2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/sched.h>
21 #include <linux/tty.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial_core.h>
24 #include <linux/bootmem.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27 #include <linux/time.h>
28 #include <linux/timex.h>
29 #include <linux/clocksource.h>
31 #include <asm/arch/udc.h>
32 #include <asm/hardware.h>
33 #include <asm/uaccess.h>
35 #include <asm/pgtable.h>
39 #include <asm/mach/map.h>
40 #include <asm/mach/irq.h>
41 #include <asm/mach/time.h>
43 /*************************************************************************
44 * IXP4xx chipset I/O mapping
45 *************************************************************************/
46 static struct map_desc ixp4xx_io_desc[] __initdata = {
47 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
48 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
49 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
50 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
52 }, { /* Expansion Bus Config Registers */
53 .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
54 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
55 .length = IXP4XX_EXP_CFG_REGION_SIZE,
57 }, { /* PCI Registers */
58 .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
59 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
60 .length = IXP4XX_PCI_CFG_REGION_SIZE,
63 #ifdef CONFIG_DEBUG_LL
64 { /* Debug UART mapping */
65 .virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
66 .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
67 .length = IXP4XX_DEBUG_UART_REGION_SIZE,
73 void __init ixp4xx_map_io(void)
75 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
79 /*************************************************************************
80 * IXP4xx chipset IRQ handling
82 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
83 * (be it PCI or something else) configures that GPIO line
85 **************************************************************************/
86 enum ixp4xx_irq_type {
87 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
90 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
91 static unsigned long long ixp4xx_irq_edge = 0;
94 * IRQ -> GPIO mapping table
96 static signed char irq2gpio[32] = {
97 -1, -1, -1, -1, -1, -1, 0, 1,
98 -1, -1, -1, -1, -1, -1, -1, -1,
99 -1, -1, -1, 2, 3, 4, 5, 6,
100 7, 8, 9, 10, 11, 12, -1, -1,
103 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
105 int line = irq2gpio[irq];
107 enum ixp4xx_irq_type irq_type;
108 volatile u32 *int_reg;
118 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
119 irq_type = IXP4XX_IRQ_EDGE;
122 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
123 irq_type = IXP4XX_IRQ_EDGE;
126 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
127 irq_type = IXP4XX_IRQ_EDGE;
130 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
131 irq_type = IXP4XX_IRQ_LEVEL;
134 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
135 irq_type = IXP4XX_IRQ_LEVEL;
141 if (irq_type == IXP4XX_IRQ_EDGE)
142 ixp4xx_irq_edge |= (1 << irq);
144 ixp4xx_irq_edge &= ~(1 << irq);
146 if (line >= 8) { /* pins 8-15 */
148 int_reg = IXP4XX_GPIO_GPIT2R;
149 } else { /* pins 0-7 */
150 int_reg = IXP4XX_GPIO_GPIT1R;
153 /* Clear the style for the appropriate pin */
154 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
155 (line * IXP4XX_GPIO_STYLE_SIZE));
157 *IXP4XX_GPIO_GPISR = (1 << line);
159 /* Set the new style */
160 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
162 /* Configure the line as an input */
163 gpio_line_config(line, IXP4XX_GPIO_IN);
168 static void ixp4xx_irq_mask(unsigned int irq)
170 if (cpu_is_ixp46x() && irq >= 32)
171 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
173 *IXP4XX_ICMR &= ~(1 << irq);
176 static void ixp4xx_irq_ack(unsigned int irq)
178 int line = (irq < 32) ? irq2gpio[irq] : -1;
181 *IXP4XX_GPIO_GPISR = (1 << line);
185 * Level triggered interrupts on GPIO lines can only be cleared when the
186 * interrupt condition disappears.
188 static void ixp4xx_irq_unmask(unsigned int irq)
190 if (!(ixp4xx_irq_edge & (1 << irq)))
193 if (cpu_is_ixp46x() && irq >= 32)
194 *IXP4XX_ICMR2 |= (1 << (irq - 32));
196 *IXP4XX_ICMR |= (1 << irq);
199 static struct irq_chip ixp4xx_irq_chip = {
201 .ack = ixp4xx_irq_ack,
202 .mask = ixp4xx_irq_mask,
203 .unmask = ixp4xx_irq_unmask,
204 .set_type = ixp4xx_set_irq_type,
207 void __init ixp4xx_init_irq(void)
211 /* Route all sources to IRQ instead of FIQ */
214 /* Disable all interrupt */
217 if (cpu_is_ixp46x()) {
218 /* Route upper 32 sources to IRQ instead of FIQ */
219 *IXP4XX_ICLR2 = 0x00;
221 /* Disable upper 32 interrupts */
222 *IXP4XX_ICMR2 = 0x00;
225 /* Default to all level triggered */
226 for(i = 0; i < NR_IRQS; i++) {
227 set_irq_chip(i, &ixp4xx_irq_chip);
228 set_irq_handler(i, handle_level_irq);
229 set_irq_flags(i, IRQF_VALID);
234 /*************************************************************************
236 * We use OS timer1 on the CPU for the timer tick and the timestamp
237 * counter as a source of real clock ticks to account for missed jiffies.
238 *************************************************************************/
240 static unsigned volatile last_jiffy_time;
242 #define CLOCK_TICKS_PER_USEC ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
244 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
246 write_seqlock(&xtime_lock);
248 /* Clear Pending Interrupt by writing '1' to it */
249 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
252 * Catch up with the real idea of time
254 while ((signed long)(*IXP4XX_OSTS - last_jiffy_time) >= LATCH) {
256 last_jiffy_time += LATCH;
259 write_sequnlock(&xtime_lock);
264 static struct irqaction ixp4xx_timer_irq = {
265 .name = "IXP4xx Timer Tick",
266 .flags = IRQF_DISABLED | IRQF_TIMER,
267 .handler = ixp4xx_timer_interrupt,
270 static void __init ixp4xx_timer_init(void)
272 /* Clear Pending Interrupt by writing '1' to it */
273 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
275 /* Setup the Timer counter value */
276 *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
278 /* Reset time-stamp counter */
282 /* Connect the interrupt handler and enable the interrupt */
283 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
286 struct sys_timer ixp4xx_timer = {
287 .init = ixp4xx_timer_init,
290 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
292 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
294 memcpy(&ixp4xx_udc_info, info, sizeof *info);
297 static struct resource ixp4xx_udc_resources[] = {
301 .flags = IORESOURCE_MEM,
304 .start = IRQ_IXP4XX_USB,
305 .end = IRQ_IXP4XX_USB,
306 .flags = IORESOURCE_IRQ,
311 * USB device controller. The IXP4xx uses the same controller as PXA2XX,
312 * so we just use the same device.
314 static struct platform_device ixp4xx_udc_device = {
315 .name = "pxa2xx-udc",
318 .resource = ixp4xx_udc_resources,
320 .platform_data = &ixp4xx_udc_info,
324 static struct platform_device *ixp4xx_devices[] __initdata = {
328 static struct resource ixp46x_i2c_resources[] = {
332 .flags = IORESOURCE_MEM,
335 .start = IRQ_IXP4XX_I2C,
336 .end = IRQ_IXP4XX_I2C,
337 .flags = IORESOURCE_IRQ
342 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
343 * we just use the same device name.
345 static struct platform_device ixp46x_i2c_controller = {
346 .name = "IOP3xx-I2C",
349 .resource = ixp46x_i2c_resources
352 static struct platform_device *ixp46x_devices[] __initdata = {
353 &ixp46x_i2c_controller
356 unsigned long ixp4xx_exp_bus_size;
357 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
359 void __init ixp4xx_sys_init(void)
361 ixp4xx_exp_bus_size = SZ_16M;
363 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
365 if (cpu_is_ixp46x()) {
368 platform_add_devices(ixp46x_devices,
369 ARRAY_SIZE(ixp46x_devices));
371 for (region = 0; region < 7; region++) {
372 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
373 ixp4xx_exp_bus_size = SZ_32M;
379 printk("IXP4xx: Using %luMiB expansion bus window size\n",
380 ixp4xx_exp_bus_size >> 20);
383 cycle_t ixp4xx_get_cycles(void)
388 static struct clocksource clocksource_ixp4xx = {
391 .read = ixp4xx_get_cycles,
392 .mask = CLOCKSOURCE_MASK(32),
397 unsigned long ixp4xx_timer_freq = FREQ;
398 static int __init ixp4xx_clocksource_init(void)
400 clocksource_ixp4xx.mult =
401 clocksource_hz2mult(ixp4xx_timer_freq,
402 clocksource_ixp4xx.shift);
403 clocksource_register(&clocksource_ixp4xx);
408 device_initcall(ixp4xx_clocksource_init);