2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
35 #include <mach/irqs.h>
36 #include <mach/hardware.h>
37 #include <mach/common.h>
43 * Resource definition for the MXC IrDA
45 static struct resource mxc_irda_resources[] = {
47 .start = UART3_BASE_ADDR,
48 .end = UART3_BASE_ADDR + SZ_4K - 1,
49 .flags = IORESOURCE_MEM,
52 .start = MXC_INT_UART3,
54 .flags = IORESOURCE_IRQ,
58 /* Platform Data for MXC IrDA */
59 struct platform_device mxc_irda_device = {
62 .num_resources = ARRAY_SIZE(mxc_irda_resources),
63 .resource = mxc_irda_resources,
67 * General Purpose Timer
68 * - i.MX1: 2 timer (slighly different register handling)
73 /* We use gpt0 as system timer, so do not add a device for this one */
75 static struct resource timer1_resources[] = {
77 .start = GPT2_BASE_ADDR,
78 .end = GPT2_BASE_ADDR + 0x17,
79 .flags = IORESOURCE_MEM
82 .start = MXC_INT_GPT2,
84 .flags = IORESOURCE_IRQ,
88 struct platform_device mxc_gpt1 = {
91 .num_resources = ARRAY_SIZE(timer1_resources),
92 .resource = timer1_resources
95 static struct resource timer2_resources[] = {
97 .start = GPT3_BASE_ADDR,
98 .end = GPT3_BASE_ADDR + 0x17,
99 .flags = IORESOURCE_MEM
102 .start = MXC_INT_GPT3,
104 .flags = IORESOURCE_IRQ,
108 struct platform_device mxc_gpt2 = {
111 .num_resources = ARRAY_SIZE(timer2_resources),
112 .resource = timer2_resources
115 #ifdef CONFIG_MACH_MX27
116 static struct resource timer3_resources[] = {
118 .start = GPT4_BASE_ADDR,
119 .end = GPT4_BASE_ADDR + 0x17,
120 .flags = IORESOURCE_MEM
123 .start = MXC_INT_GPT4,
125 .flags = IORESOURCE_IRQ,
129 struct platform_device mxc_gpt3 = {
132 .num_resources = ARRAY_SIZE(timer3_resources),
133 .resource = timer3_resources
136 static struct resource timer4_resources[] = {
138 .start = GPT5_BASE_ADDR,
139 .end = GPT5_BASE_ADDR + 0x17,
140 .flags = IORESOURCE_MEM
143 .start = MXC_INT_GPT5,
145 .flags = IORESOURCE_IRQ,
149 struct platform_device mxc_gpt4 = {
152 .num_resources = ARRAY_SIZE(timer4_resources),
153 .resource = timer4_resources
156 static struct resource timer5_resources[] = {
158 .start = GPT6_BASE_ADDR,
159 .end = GPT6_BASE_ADDR + 0x17,
160 .flags = IORESOURCE_MEM
163 .start = MXC_INT_GPT6,
165 .flags = IORESOURCE_IRQ,
169 struct platform_device mxc_gpt5 = {
172 .num_resources = ARRAY_SIZE(timer5_resources),
173 .resource = timer5_resources
183 static struct resource mxc_wdt_resources[] = {
185 .start = WDOG_BASE_ADDR,
186 .end = WDOG_BASE_ADDR + 0x30,
187 .flags = IORESOURCE_MEM,
191 struct platform_device mxc_wdt = {
194 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
195 .resource = mxc_wdt_resources,
198 static struct resource mxc_w1_master_resources[] = {
200 .start = OWIRE_BASE_ADDR,
201 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
202 .flags = IORESOURCE_MEM,
206 struct platform_device mxc_w1_master_device = {
209 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
210 .resource = mxc_w1_master_resources,
213 static struct resource mxc_nand_resources[] = {
215 .start = NFC_BASE_ADDR,
216 .end = NFC_BASE_ADDR + 0xfff,
217 .flags = IORESOURCE_MEM
219 .start = MXC_INT_NANDFC,
220 .end = MXC_INT_NANDFC,
221 .flags = IORESOURCE_IRQ
225 struct platform_device mxc_nand_device = {
228 .num_resources = ARRAY_SIZE(mxc_nand_resources),
229 .resource = mxc_nand_resources,
235 * - i.MX1: the basic controller
236 * - i.MX21: to be checked
237 * - i.MX27: like i.MX1, with slightly variations
239 static struct resource mxc_fb[] = {
241 .start = LCDC_BASE_ADDR,
242 .end = LCDC_BASE_ADDR + 0xFFF,
243 .flags = IORESOURCE_MEM,
246 .start = MXC_INT_LCDC,
248 .flags = IORESOURCE_IRQ,
253 struct platform_device mxc_fb_device = {
256 .num_resources = ARRAY_SIZE(mxc_fb),
259 .coherent_dma_mask = 0xFFFFFFFF,
264 #ifdef CONFIG_MACH_MX27
265 static struct resource mxc_fec_resources[] = {
267 .start = FEC_BASE_ADDR,
268 .end = FEC_BASE_ADDR + 0xfff,
269 .flags = IORESOURCE_MEM
271 .start = MXC_INT_FEC,
273 .flags = IORESOURCE_IRQ
277 struct platform_device mxc_fec_device = {
280 .num_resources = ARRAY_SIZE(mxc_fec_resources),
281 .resource = mxc_fec_resources,
285 static struct resource mxc_i2c_1_resources[] = {
287 .start = I2C_BASE_ADDR,
288 .end = I2C_BASE_ADDR + 0x0fff,
289 .flags = IORESOURCE_MEM
292 .start = MXC_INT_I2C,
294 .flags = IORESOURCE_IRQ
298 struct platform_device mxc_i2c_device0 = {
301 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
302 .resource = mxc_i2c_1_resources
305 #ifdef CONFIG_MACH_MX27
306 static struct resource mxc_i2c_2_resources[] = {
308 .start = I2C2_BASE_ADDR,
309 .end = I2C2_BASE_ADDR + 0x0fff,
310 .flags = IORESOURCE_MEM
313 .start = MXC_INT_I2C2,
315 .flags = IORESOURCE_IRQ
319 struct platform_device mxc_i2c_device1 = {
322 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
323 .resource = mxc_i2c_2_resources
327 static struct resource mxc_pwm_resources[] = {
329 .start = PWM_BASE_ADDR,
330 .end = PWM_BASE_ADDR + 0x0fff,
331 .flags = IORESOURCE_MEM
334 .start = MXC_INT_PWM,
336 .flags = IORESOURCE_IRQ,
340 struct platform_device mxc_pwm_device = {
343 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
344 .resource = mxc_pwm_resources
348 * Resource definition for the MXC SDHC
350 static struct resource mxc_sdhc1_resources[] = {
352 .start = SDHC1_BASE_ADDR,
353 .end = SDHC1_BASE_ADDR + SZ_4K - 1,
354 .flags = IORESOURCE_MEM,
357 .start = MXC_INT_SDHC1,
358 .end = MXC_INT_SDHC1,
359 .flags = IORESOURCE_IRQ,
362 .start = DMA_REQ_SDHC1,
363 .end = DMA_REQ_SDHC1,
364 .flags = IORESOURCE_DMA
368 static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
370 struct platform_device mxc_sdhc_device0 = {
374 .dma_mask = &mxc_sdhc1_dmamask,
375 .coherent_dma_mask = 0xffffffff,
377 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
378 .resource = mxc_sdhc1_resources,
381 static struct resource mxc_sdhc2_resources[] = {
383 .start = SDHC2_BASE_ADDR,
384 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
385 .flags = IORESOURCE_MEM,
388 .start = MXC_INT_SDHC2,
389 .end = MXC_INT_SDHC2,
390 .flags = IORESOURCE_IRQ,
393 .start = DMA_REQ_SDHC2,
394 .end = DMA_REQ_SDHC2,
395 .flags = IORESOURCE_DMA
399 static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
401 struct platform_device mxc_sdhc_device1 = {
405 .dma_mask = &mxc_sdhc2_dmamask,
406 .coherent_dma_mask = 0xffffffff,
408 .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
409 .resource = mxc_sdhc2_resources,
412 /* GPIO port description */
413 static struct mxc_gpio_port imx_gpio_ports[] = {
415 .chip.label = "gpio-0",
417 .base = IO_ADDRESS(GPIO_BASE_ADDR),
418 .virtual_irq_start = MXC_GPIO_IRQ_START,
421 .chip.label = "gpio-1",
422 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
423 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
426 .chip.label = "gpio-2",
427 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
428 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
431 .chip.label = "gpio-3",
432 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
433 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
436 .chip.label = "gpio-4",
437 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
438 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
441 .chip.label = "gpio-5",
442 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
443 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
447 int __init mxc_register_gpios(void)
449 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));