arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/pm.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/pm.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/sysfs.h>
  44 #include <linux/module.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48 #include <asm/atomic.h>
  49 #include <asm/mach/time.h>
  50 #include <asm/mach/irq.h>
  51 #include <asm/mach-types.h>
  52
  53 #include <asm/arch/irqs.h>
  54 #include <asm/arch/clock.h>
  55 #include <asm/arch/sram.h>
  56 #include <asm/arch/tc.h>
  57 #include <asm/arch/pm.h>
  58 #include <asm/arch/mux.h>
  59 #include <asm/arch/tps65010.h>
  60 #include <asm/arch/dma.h>
  61 #include <asm/arch/dsp_common.h>
  62 #include <asm/arch/dmtimer.h>
  63
  64 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  65 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  66 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  67 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  68 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  69 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  70
  71 static unsigned short enable_dyn_sleep = 1;
  72
  73 static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
  74 {
  75         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  76 }
  77
  78 static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
  79                                               const char * buf,
  80                                               size_t n)
  81 {
  82         unsigned short value;
  83         if (sscanf(buf, "%hu", &value) != 1 ||
  84             (value != 0 && value != 1)) {
  85                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  86                 return -EINVAL;
  87         }
  88         enable_dyn_sleep = value;
  89         return n;
  90 }
  91
  92 static struct subsys_attribute sleep_while_idle_attr = {
  93         .attr   = {
  94                 .name = __stringify(sleep_while_idle),
  95                 .mode = 0644,
  96         },
  97         .show   = omap_pm_sleep_while_idle_show,
  98         .store  = omap_pm_sleep_while_idle_store,
  99 };
 100
 101 extern struct subsystem power_subsys;
 102 static void (*omap_sram_idle)(void) = NULL;
 103 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 104
 105 /*
 106  * Let's power down on idle, but only if we are really
 107  * idle, because once we start down the path of
 108  * going idle we continue to do idle even if we get
 109  * a clock tick interrupt . .
 110  */
 111 void omap_pm_idle(void)
 112 {
 113         extern __u32 arm_idlect1_mask;
 114         __u32 use_idlect1 = arm_idlect1_mask;
 115 #ifndef CONFIG_OMAP_MPU_TIMER
 116         int do_sleep;
 117 #endif
 118
 119         local_irq_disable();
 120         local_fiq_disable();
 121         if (need_resched()) {
 122                 local_fiq_enable();
 123                 local_irq_enable();
 124                 return;
 125         }
 126
 127         /*
 128          * Since an interrupt may set up a timer, we don't want to
 129          * reprogram the hardware timer with interrupts enabled.
 130          * Re-enable interrupts only after returning from idle.
 131          */
 132         timer_dyn_reprogram();
 133
 134 #ifdef CONFIG_OMAP_MPU_TIMER
 135 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 136         use_idlect1 = use_idlect1 & ~(1 << 9);
 137 #else
 138
 139         do_sleep = 0;
 140         while (enable_dyn_sleep) {
 141
 142 #ifdef CONFIG_CBUS_TAHVO_USB
 143                 extern int vbus_active;
 144                 /* Clock requirements? */
 145                 if (vbus_active)
 146                         break;
 147 #endif
 148                 do_sleep = 1;
 149                 break;
 150         }
 151
 152 #ifdef CONFIG_OMAP_DM_TIMER
 153         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 154 #endif
 155
 156         if (omap_dma_running()) {
 157                 use_idlect1 &= ~(1 << 6);
 158                 if (omap_lcd_dma_ext_running())
 159                         use_idlect1 &= ~(1 << 12);
 160         }
 161
 162         /* We should be able to remove the do_sleep variable and multiple
 163          * tests above as soon as drivers, timer and DMA code have been fixed.
 164          * Even the sleep block count should become obsolete. */
 165         if ((use_idlect1 != ~0) || !do_sleep) {
 166
 167                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 168                 if (cpu_is_omap1510())
 169                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 170                 else
 171                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 172                 omap_writel(use_idlect1, ARM_IDLECT1);
 173                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 174                 omap_writel(saved_idlect1, ARM_IDLECT1);
 175
 176                 local_fiq_enable();
 177                 local_irq_enable();
 178                 return;
 179         }
 180         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 181                           omap_readl(ARM_IDLECT2));
 182 #endif
 183
 184         local_fiq_enable();
 185         local_irq_enable();
 186 }
 187
 188 /*
 189  * Configuration of the wakeup event is board specific. For the
 190  * moment we put it into this helper function. Later it may move
 191  * to board specific files.
 192  */
 193 static void omap_pm_wakeup_setup(void)
 194 {
 195         u32 level1_wake = 0;
 196         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 197
 198         /*
 199          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 200          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 201          * drivers must still separately call omap_set_gpio_wakeup() to
 202          * wake up to a GPIO interrupt.
 203          */
 204         if (cpu_is_omap730())
 205                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 206                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 207         else if (cpu_is_omap1510())
 208                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 209                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 210         else if (cpu_is_omap16xx())
 211                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 212                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 213
 214         omap_writel(~level1_wake, OMAP_IH1_MIR);
 215
 216         if (cpu_is_omap730()) {
 217                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 218                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 219                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 220                                 OMAP_IH2_1_MIR);
 221         } else if (cpu_is_omap1510()) {
 222                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 223                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 224         } else if (cpu_is_omap16xx()) {
 225                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 226                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 227
 228                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 229                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 230                             OMAP_IH2_1_MIR);
 231                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 232                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 233         }
 234
 235         /*  New IRQ agreement, recalculate in cascade order */
 236         omap_writel(1, OMAP_IH2_CONTROL);
 237         omap_writel(1, OMAP_IH1_CONTROL);
 238 }
 239
 240 #define EN_DSPCK        13      /* ARM_CKCTL */
 241 #define EN_APICK        6       /* ARM_IDLECT2 */
 242
 243 void omap_pm_suspend(void)
 244 {
 245         unsigned long arg0 = 0, arg1 = 0;
 246
 247         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 248
 249         omap_serial_wake_trigger(1);
 250
 251         if (machine_is_omap_osk()) {
 252                 /* Stop LED1 (D9) blink */
 253                 tps65010_set_led(LED1, OFF);
 254         }
 255
 256         omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 257
 258         /*
 259          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 260          */
 261
 262         local_irq_disable();
 263         local_fiq_disable();
 264
 265         /*
 266          * Step 2: save registers
 267          *
 268          * The omap is a strange/beautiful device. The caches, memory
 269          * and register state are preserved across power saves.
 270          * We have to save and restore very little register state to
 271          * idle the omap.
 272          *
 273          * Save interrupt, MPUI, ARM and UPLD control registers.
 274          */
 275
 276         if (cpu_is_omap730()) {
 277                 MPUI730_SAVE(OMAP_IH1_MIR);
 278                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 279                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 280                 MPUI730_SAVE(MPUI_CTRL);
 281                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 282                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 283                 MPUI730_SAVE(EMIFS_CONFIG);
 284                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 285
 286         } else if (cpu_is_omap1510()) {
 287                 MPUI1510_SAVE(OMAP_IH1_MIR);
 288                 MPUI1510_SAVE(OMAP_IH2_MIR);
 289                 MPUI1510_SAVE(MPUI_CTRL);
 290                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 291                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 292                 MPUI1510_SAVE(EMIFS_CONFIG);
 293                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 294         } else if (cpu_is_omap16xx()) {
 295                 MPUI1610_SAVE(OMAP_IH1_MIR);
 296                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 297                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 298                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 299                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 300                 MPUI1610_SAVE(MPUI_CTRL);
 301                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 302                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 303                 MPUI1610_SAVE(EMIFS_CONFIG);
 304                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 305         }
 306
 307         ARM_SAVE(ARM_CKCTL);
 308         ARM_SAVE(ARM_IDLECT1);
 309         ARM_SAVE(ARM_IDLECT2);
 310         if (!(cpu_is_omap1510()))
 311                 ARM_SAVE(ARM_IDLECT3);
 312         ARM_SAVE(ARM_EWUPCT);
 313         ARM_SAVE(ARM_RSTCT1);
 314         ARM_SAVE(ARM_RSTCT2);
 315         ARM_SAVE(ARM_SYSST);
 316         ULPD_SAVE(ULPD_CLOCK_CTRL);
 317         ULPD_SAVE(ULPD_STATUS_REQ);
 318
 319         /* (Step 3 removed - we now allow deep sleep by default) */
 320
 321         /*
 322          * Step 4: OMAP DSP Shutdown
 323          */
 324
 325         /* stop DSP */
 326         omap_dsp_pm_suspend();
 327
 328         /* shut down dsp_ck */
 329         omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 330
 331         /* temporarily enabling api_ck to access DSP registers */
 332         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 333
 334         /* save DSP registers */
 335         DSP_SAVE(DSP_IDLECT2);
 336
 337         /* Stop all DSP domain clocks */
 338         __raw_writew(0, DSP_IDLECT2);
 339
 340         /*
 341          * Step 5: Wakeup Event Setup
 342          */
 343
 344         omap_pm_wakeup_setup();
 345
 346         /*
 347          * Step 6: ARM and Traffic controller shutdown
 348          */
 349
 350         /* disable ARM watchdog */
 351         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 352         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 353
 354         /*
 355          * Step 6b: ARM and Traffic controller shutdown
 356          *
 357          * Step 6 continues here. Prepare jump to power management
 358          * assembly code in internal SRAM.
 359          *
 360          * Since the omap_cpu_suspend routine has been copied to
 361          * SRAM, we'll do an indirect procedure call to it and pass the
 362          * contents of arm_idlect1 and arm_idlect2 so it can restore
 363          * them when it wakes up and it will return.
 364          */
 365
 366         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 367         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 368
 369         /*
 370          * Step 6c: ARM and Traffic controller shutdown
 371          *
 372          * Jump to assembly code. The processor will stay there
 373          * until wake up.
 374          */
 375         omap_sram_suspend(arg0, arg1);
 376
 377         /*
 378          * If we are here, processor is woken up!
 379          */
 380
 381         /*
 382          * Restore DSP clocks
 383          */
 384
 385         /* again temporarily enabling api_ck to access DSP registers */
 386         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 387
 388         /* Restore DSP domain clocks */
 389         DSP_RESTORE(DSP_IDLECT2);
 390
 391         /* resume DSP */
 392         omap_dsp_pm_resume();
 393
 394         /*
 395          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 396          */
 397
 398         if (!(cpu_is_omap1510()))
 399                 ARM_RESTORE(ARM_IDLECT3);
 400         ARM_RESTORE(ARM_CKCTL);
 401         ARM_RESTORE(ARM_EWUPCT);
 402         ARM_RESTORE(ARM_RSTCT1);
 403         ARM_RESTORE(ARM_RSTCT2);
 404         ARM_RESTORE(ARM_SYSST);
 405         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 406         ULPD_RESTORE(ULPD_STATUS_REQ);
 407
 408         if (cpu_is_omap730()) {
 409                 MPUI730_RESTORE(EMIFS_CONFIG);
 410                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 411                 MPUI730_RESTORE(OMAP_IH1_MIR);
 412                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 413                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 414         } else if (cpu_is_omap1510()) {
 415                 MPUI1510_RESTORE(MPUI_CTRL);
 416                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 417                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 418                 MPUI1510_RESTORE(EMIFS_CONFIG);
 419                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 420                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 421                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 422         } else if (cpu_is_omap16xx()) {
 423                 MPUI1610_RESTORE(MPUI_CTRL);
 424                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 425                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 426                 MPUI1610_RESTORE(EMIFS_CONFIG);
 427                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 428
 429                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 430                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 431                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 432                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 433                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 434         }
 435
 436         omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 437
 438         /*
 439          * Reenable interrupts
 440          */
 441
 442         local_irq_enable();
 443         local_fiq_enable();
 444
 445         omap_serial_wake_trigger(0);
 446
 447         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 448
 449         if (machine_is_omap_osk()) {
 450                 /* Let LED1 (D9) blink again */
 451                 tps65010_set_led(LED1, BLINK);
 452         }
 453 }
 454
 455 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 456 static int g_read_completed;
 457
 458 /*
 459  * Read system PM registers for debugging
 460  */
 461 static int omap_pm_read_proc(
 462         char *page_buffer,
 463         char **my_first_byte,
 464         off_t virtual_start,
 465         int length,
 466         int *eof,
 467         void *data)
 468 {
 469         int my_buffer_offset = 0;
 470         char * const my_base = page_buffer;
 471
 472         ARM_SAVE(ARM_CKCTL);
 473         ARM_SAVE(ARM_IDLECT1);
 474         ARM_SAVE(ARM_IDLECT2);
 475         if (!(cpu_is_omap1510()))
 476                 ARM_SAVE(ARM_IDLECT3);
 477         ARM_SAVE(ARM_EWUPCT);
 478         ARM_SAVE(ARM_RSTCT1);
 479         ARM_SAVE(ARM_RSTCT2);
 480         ARM_SAVE(ARM_SYSST);
 481
 482         ULPD_SAVE(ULPD_IT_STATUS);
 483         ULPD_SAVE(ULPD_CLOCK_CTRL);
 484         ULPD_SAVE(ULPD_SOFT_REQ);
 485         ULPD_SAVE(ULPD_STATUS_REQ);
 486         ULPD_SAVE(ULPD_DPLL_CTRL);
 487         ULPD_SAVE(ULPD_POWER_CTRL);
 488
 489         if (cpu_is_omap730()) {
 490                 MPUI730_SAVE(MPUI_CTRL);
 491                 MPUI730_SAVE(MPUI_DSP_STATUS);
 492                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 493                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 494                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 495                 MPUI730_SAVE(EMIFS_CONFIG);
 496         } else if (cpu_is_omap1510()) {
 497                 MPUI1510_SAVE(MPUI_CTRL);
 498                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 499                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 500                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 501                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 502                 MPUI1510_SAVE(EMIFS_CONFIG);
 503         } else if (cpu_is_omap16xx()) {
 504                 MPUI1610_SAVE(MPUI_CTRL);
 505                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 506                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 507                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 508                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 509                 MPUI1610_SAVE(EMIFS_CONFIG);
 510         }
 511
 512         if (virtual_start == 0) {
 513                 g_read_completed = 0;
 514
 515                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 516                    "ARM_CKCTL_REG:            0x%-8x     \n"
 517                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 518                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 519                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 520                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 521                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 522                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 523                    "ARM_SYSST_REG:            0x%-8x     \n"
 524                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 525                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 526                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 527                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 528                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 529                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 530                    ARM_SHOW(ARM_CKCTL),
 531                    ARM_SHOW(ARM_IDLECT1),
 532                    ARM_SHOW(ARM_IDLECT2),
 533                    ARM_SHOW(ARM_IDLECT3),
 534                    ARM_SHOW(ARM_EWUPCT),
 535                    ARM_SHOW(ARM_RSTCT1),
 536                    ARM_SHOW(ARM_RSTCT2),
 537                    ARM_SHOW(ARM_SYSST),
 538                    ULPD_SHOW(ULPD_IT_STATUS),
 539                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 540                    ULPD_SHOW(ULPD_SOFT_REQ),
 541                    ULPD_SHOW(ULPD_DPLL_CTRL),
 542                    ULPD_SHOW(ULPD_STATUS_REQ),
 543                    ULPD_SHOW(ULPD_POWER_CTRL));
 544
 545                 if (cpu_is_omap730()) {
 546                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 547                            "MPUI730_CTRL_REG         0x%-8x \n"
 548                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 549                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 550                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 551                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 552                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 553                            MPUI730_SHOW(MPUI_CTRL),
 554                            MPUI730_SHOW(MPUI_DSP_STATUS),
 555                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 556                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 557                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 558                            MPUI730_SHOW(EMIFS_CONFIG));
 559                 } else if (cpu_is_omap1510()) {
 560                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 561                            "MPUI1510_CTRL_REG             0x%-8x \n"
 562                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 563                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 564                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 565                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 566                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 567                            MPUI1510_SHOW(MPUI_CTRL),
 568                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 569                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 570                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 571                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 572                            MPUI1510_SHOW(EMIFS_CONFIG));
 573                 } else if (cpu_is_omap16xx()) {
 574                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 575                            "MPUI1610_CTRL_REG             0x%-8x \n"
 576                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 577                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 578                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 579                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 580                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 581                            MPUI1610_SHOW(MPUI_CTRL),
 582                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 583                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 584                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 585                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 586                            MPUI1610_SHOW(EMIFS_CONFIG));
 587                 }
 588
 589                 g_read_completed++;
 590         } else if (g_read_completed >= 1) {
 591                  *eof = 1;
 592                  return 0;
 593         }
 594         g_read_completed++;
 595
 596         *my_first_byte = page_buffer;
 597         return  my_buffer_offset;
 598 }
 599
 600 static void omap_pm_init_proc(void)
 601 {
 602         struct proc_dir_entry *entry;
 603
 604         entry = create_proc_read_entry("driver/omap_pm",
 605                                        S_IWUSR | S_IRUGO, NULL,
 606                                        omap_pm_read_proc, NULL);
 607 }
 608
 609 #endif /* DEBUG && CONFIG_PROC_FS */
 610
 611 static void (*saved_idle)(void) = NULL;
 612
 613 /*
 614  *      omap_pm_prepare - Do preliminary suspend work.
 615  *      @state:         suspend state we're entering.
 616  *
 617  */
 618 static int omap_pm_prepare(suspend_state_t state)
 619 {
 620         int error = 0;
 621
 622         /* We cannot sleep in idle until we have resumed */
 623         saved_idle = pm_idle;
 624         pm_idle = NULL;
 625
 626         switch (state)
 627         {
 628         case PM_SUSPEND_STANDBY:
 629         case PM_SUSPEND_MEM:
 630                 break;
 631
 632         case PM_SUSPEND_DISK:
 633                 return -ENOTSUPP;
 634
 635         default:
 636                 return -EINVAL;
 637         }
 638
 639         return error;
 640 }
 641
 642
 643 /*
 644  *      omap_pm_enter - Actually enter a sleep state.
 645  *      @state:         State we're entering.
 646  *
 647  */
 648
 649 static int omap_pm_enter(suspend_state_t state)
 650 {
 651         switch (state)
 652         {
 653         case PM_SUSPEND_STANDBY:
 654         case PM_SUSPEND_MEM:
 655                 omap_pm_suspend();
 656                 break;
 657
 658         case PM_SUSPEND_DISK:
 659                 return -ENOTSUPP;
 660
 661         default:
 662                 return -EINVAL;
 663         }
 664
 665         return 0;
 666 }
 667
 668
 669 /**
 670  *      omap_pm_finish - Finish up suspend sequence.
 671  *      @state:         State we're coming out of.
 672  *
 673  *      This is called after we wake back up (or if entering the sleep state
 674  *      failed).
 675  */
 676
 677 static int omap_pm_finish(suspend_state_t state)
 678 {
 679         pm_idle = saved_idle;
 680         return 0;
 681 }
 682
 683
 684 static irqreturn_t  omap_wakeup_interrupt(int  irq, void *  dev,
 685                                      struct pt_regs *  regs)
 686 {
 687         return IRQ_HANDLED;
 688 }
 689
 690 static struct irqaction omap_wakeup_irq = {
 691         .name           = "peripheral wakeup",
 692         .flags          = SA_INTERRUPT,
 693         .handler        = omap_wakeup_interrupt
 694 };
 695
 696
 697
 698 static struct pm_ops omap_pm_ops ={
 699         .pm_disk_mode = 0,
 700         .prepare        = omap_pm_prepare,
 701         .enter          = omap_pm_enter,
 702         .finish         = omap_pm_finish,
 703 };
 704
 705 static int __init omap_pm_init(void)
 706 {
 707         printk("Power Management for TI OMAP.\n");
 708
 709         /*
 710          * We copy the assembler sleep/wakeup routines to SRAM.
 711          * These routines need to be in SRAM as that's the only
 712          * memory the MPU can see when it wakes up.
 713          */
 714         if (cpu_is_omap730()) {
 715                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
 716                                                 omap730_idle_loop_suspend_sz);
 717                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 718                                                    omap730_cpu_suspend_sz);
 719         } else if (cpu_is_omap1510()) {
 720                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
 721                                                 omap1510_idle_loop_suspend_sz);
 722                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 723                                                    omap1510_cpu_suspend_sz);
 724         } else if (cpu_is_omap16xx()) {
 725                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
 726                                                 omap1610_idle_loop_suspend_sz);
 727                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 728                                                    omap1610_cpu_suspend_sz);
 729         }
 730
 731         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
 732                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 733                 return -ENODEV;
 734         }
 735
 736         pm_idle = omap_pm_idle;
 737
 738         if (cpu_is_omap730())
 739                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 740         else if (cpu_is_omap16xx())
 741                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 742
 743 #if 0
 744         /* --- BEGIN BOARD-DEPENDENT CODE --- */
 745         /* Sleepx mask direction */
 746         omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
 747         /* Unmask sleepx signal */
 748         omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 749         /* --- END BOARD-DEPENDENT CODE --- */
 750 #endif
 751
 752         /* Program new power ramp-up time
 753          * (0 for most boards since we don't lower voltage when in deep sleep)
 754          */
 755         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 756
 757         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 758         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 759
 760         /* Configure IDLECT3 */
 761         if (cpu_is_omap730())
 762                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 763         else if (cpu_is_omap16xx())
 764                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 765
 766         pm_set_ops(&omap_pm_ops);
 767
 768 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 769         omap_pm_init_proc();
 770 #endif
 771
 772         subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 773
 774         if (cpu_is_omap16xx()) {
 775                 /* configure LOW_PWR pin */
 776                 omap_cfg_reg(T20_1610_LOW_PWR);
 777         }
 778
 779         return 0;
 780 }
 781 __initcall(omap_pm_init);