2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Cleaned up and modified to use omap shared clock framework by
9 * Tony Lindgren <tony@atomide.com>
11 * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
12 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/device.h>
21 #include <linux/list.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sram.h>
31 #include "prcm-regs.h"
35 //#define DOWN_VARIABLE_DPLL 1 /* Experimental */
37 static struct prcm_config *curr_prcm_set;
38 static u32 curr_perf_level = PRCM_FULL_SPEED;
39 static struct clk *vclk;
40 static struct clk *sclk;
42 /*-------------------------------------------------------------------------
43 * Omap2 specific clock functions
44 *-------------------------------------------------------------------------*/
46 /* Recalculate SYST_CLK */
47 static void omap2_sys_clk_recalc(struct clk * clk)
49 u32 div = PRCM_CLKSRC_CTRL;
50 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
51 div >>= clk->rate_offset;
52 clk->rate = (clk->parent->rate / div);
56 static u32 omap2_get_dpll_rate(struct clk * tclk)
59 int dpll_mult, dpll_div, amult;
61 dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
62 dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
63 dpll_clk = (long long)tclk->parent->rate * dpll_mult;
64 do_div(dpll_clk, dpll_div + 1);
65 amult = CM_CLKSEL2_PLL & 0x3;
71 static void omap2_followparent_recalc(struct clk *clk)
73 followparent_recalc(clk);
76 static void omap2_propagate_rate(struct clk * clk)
78 if (!(clk->flags & RATE_FIXED))
79 clk->rate = clk->parent->rate;
84 /* Enable an APLL if off */
85 static void omap2_clk_fixed_enable(struct clk *clk)
89 if (clk->enable_bit == 0xff) /* Parent will do it */
94 if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
97 cval &= ~(0x3 << clk->enable_bit);
98 cval |= (0x3 << clk->enable_bit);
101 if (clk == &apll96_ck)
103 else if (clk == &apll54_ck)
106 while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */
114 /* Enables clock without considering parent dependencies or use count
115 * REVISIT: Maybe change this to use clk->enable like on omap1?
117 static int _omap2_clk_enable(struct clk * clk)
121 if (clk->flags & ALWAYS_ENABLED)
124 if (unlikely(clk->enable_reg == 0)) {
125 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
130 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
131 omap2_clk_fixed_enable(clk);
135 regval32 = __raw_readl(clk->enable_reg);
136 regval32 |= (1 << clk->enable_bit);
137 __raw_writel(regval32, clk->enable_reg);
144 static void omap2_clk_fixed_disable(struct clk *clk)
148 if(clk->enable_bit == 0xff) /* let parent off do it */
152 cval &= ~(0x3 << clk->enable_bit);
156 /* Disables clock without considering parent dependencies or use count */
157 static void _omap2_clk_disable(struct clk *clk)
161 if (clk->enable_reg == 0)
164 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
165 omap2_clk_fixed_disable(clk);
169 regval32 = __raw_readl(clk->enable_reg);
170 regval32 &= ~(1 << clk->enable_bit);
171 __raw_writel(regval32, clk->enable_reg);
175 static int omap2_clk_enable(struct clk *clk)
179 if (clk->usecount++ == 0) {
180 if (likely((u32)clk->parent))
181 ret = omap2_clk_enable(clk->parent);
183 if (unlikely(ret != 0)) {
188 ret = _omap2_clk_enable(clk);
190 if (unlikely(ret != 0) && clk->parent) {
191 omap2_clk_disable(clk->parent);
199 static void omap2_clk_disable(struct clk *clk)
201 if (clk->usecount > 0 && !(--clk->usecount)) {
202 _omap2_clk_disable(clk);
203 if (likely((u32)clk->parent))
204 omap2_clk_disable(clk->parent);
209 * Uses the current prcm set to tell if a rate is valid.
210 * You can go slower, but not faster within a given rate set.
212 static u32 omap2_dpll_round_rate(unsigned long target_rate)
216 if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */
217 high = curr_prcm_set->dpll_speed * 2;
218 low = curr_prcm_set->dpll_speed;
219 } else { /* DPLL clockout x 2 */
220 high = curr_prcm_set->dpll_speed;
221 low = curr_prcm_set->dpll_speed / 2;
224 #ifdef DOWN_VARIABLE_DPLL
225 if (target_rate > high)
230 if (target_rate > low)
239 * Used for clocks that are part of CLKSEL_xyz governed clocks.
240 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
242 static void omap2_clksel_recalc(struct clk * clk)
244 u32 fixed = 0, div = 0;
246 if (clk == &dpll_ck) {
247 clk->rate = omap2_get_dpll_rate(clk);
252 if (clk == &iva1_mpu_int_ifck) {
257 if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
258 clk->rate = sys_ck.rate;
263 div = omap2_clksel_get_divisor(clk);
269 if (unlikely(clk->rate == clk->parent->rate / div))
271 clk->rate = clk->parent->rate / div;
274 if (unlikely(clk->flags & RATE_PROPAGATES))
279 * Finds best divider value in an array based on the source and target
280 * rates. The divider array must be sorted with smallest divider first.
282 static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
283 u32 src_rate, u32 tgt_rate)
287 if (div_array == NULL)
290 for (i=0; i < size; i++) {
291 test_rate = src_rate / *div_array;
292 if (test_rate <= tgt_rate)
297 return ~0; /* No acceptable divider */
301 * Find divisor for the given clock and target rate.
303 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
304 * they are only settable as part of virtual_prcm set.
306 static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
309 u32 gfx_div[] = {2, 3, 4};
310 u32 sysclkout_div[] = {1, 2, 4, 8, 16};
311 u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
312 u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
313 u32 best_div = ~0, asize = 0;
314 u32 *div_array = NULL;
316 switch (tclk->flags & SRC_RATE_SEL_MASK) {
322 return omap2_dpll_round_rate(target_rate);
323 case CM_SYSCLKOUT_SEL1:
325 div_array = sysclkout_div;
328 if(tclk == &dss1_fck){
329 if(tclk->parent == &core_ck){
331 div_array = dss1_div;
333 *new_div = 0; /* fixed clk */
334 return(tclk->parent->rate);
336 } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
337 if(tclk->parent == &core_ck){
339 div_array = vylnq_div;
341 *new_div = 0; /* fixed clk */
342 return(tclk->parent->rate);
348 best_div = omap2_divider_from_table(asize, div_array,
349 tclk->parent->rate, target_rate);
352 return best_div; /* signal error */
356 return (tclk->parent->rate / best_div);
359 /* Given a clock and a rate apply a clock specific rounding function */
360 static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
365 if (clk->flags & RATE_FIXED)
368 if (clk->flags & RATE_CKCTL) {
369 valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
373 if (clk->round_rate != 0)
374 return clk->round_rate(clk, rate);
380 * Check the DLL lock state, and return tue if running in unlock mode.
381 * This is needed to compenste for the shifted DLL value in unlock mode.
383 static u32 omap2_dll_force_needed(void)
385 u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */
387 if ((dll_state & (1 << 2)) == (1 << 2))
393 static u32 omap2_reprogram_sdrc(u32 level, u32 force)
395 u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
396 u32 prev = curr_perf_level, flags;
398 if ((curr_perf_level == level) && !force)
401 m_type = omap2_memory_get_type();
402 slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
403 fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
405 if (level == PRCM_HALF_SPEED) {
406 local_irq_save(flags);
407 PRCM_VOLTSETUP = 0xffff;
408 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
409 slow_dll_ctrl, m_type);
410 curr_perf_level = PRCM_HALF_SPEED;
411 local_irq_restore(flags);
413 if (level == PRCM_FULL_SPEED) {
414 local_irq_save(flags);
415 PRCM_VOLTSETUP = 0xffff;
416 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
417 fast_dll_ctrl, m_type);
418 curr_perf_level = PRCM_FULL_SPEED;
419 local_irq_restore(flags);
425 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
427 u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
429 struct prcm_config tmpset;
432 local_irq_save(flags);
433 cur_rate = omap2_get_dpll_rate(&dpll_ck);
434 mult = CM_CLKSEL2_PLL & 0x3;
436 if ((rate == (cur_rate / 2)) && (mult == 2)) {
437 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
438 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
439 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
440 } else if (rate != cur_rate) {
441 valid_rate = omap2_dpll_round_rate(rate);
442 if (valid_rate != rate)
445 if ((CM_CLKSEL2_PLL & 0x3) == 1)
446 low = curr_prcm_set->dpll_speed;
448 low = curr_prcm_set->dpll_speed / 2;
450 tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
451 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
452 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
453 tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
454 tmpset.cm_clksel2_pll &= ~0x3;
456 tmpset.cm_clksel2_pll |= 0x2;
457 mult = ((rate / 2) / 1000000);
458 done_rate = PRCM_FULL_SPEED;
460 tmpset.cm_clksel2_pll |= 0x1;
461 mult = (rate / 1000000);
462 done_rate = PRCM_HALF_SPEED;
464 tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
467 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
469 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
472 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
474 /* Force dll lock mode */
475 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
478 /* Errata: ret dll entry state */
479 omap2_init_memory_params(omap2_dll_force_needed());
480 omap2_reprogram_sdrc(done_rate, 0);
482 omap2_clksel_recalc(&dpll_ck);
486 local_irq_restore(flags);
490 /* Just return the MPU speed */
491 static void omap2_mpu_recalc(struct clk * clk)
493 clk->rate = curr_prcm_set->mpu_speed;
497 * Look for a rate equal or less than the target rate given a configuration set.
499 * What's not entirely clear is "which" field represents the key field.
500 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
501 * just uses the ARM rates.
503 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
505 struct prcm_config * ptr;
508 if (clk != &virt_prcm_set)
511 highest_rate = -EINVAL;
513 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
514 if (ptr->xtal_speed != sys_ck.rate)
517 highest_rate = ptr->mpu_speed;
519 /* Can check only after xtal frequency check */
520 if (ptr->mpu_speed <= rate)
527 * omap2_convert_field_to_div() - turn field value into integer divider
529 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
532 u32 clkout_array[] = {1, 2, 4, 8, 16};
534 if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
535 for (i = 0; i < 5; i++) {
537 return clkout_array[i];
545 * Returns the CLKSEL divider register value
546 * REVISIT: This should be cleaned up to work nicely with void __iomem *
548 static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
552 u32 reg_val, div_off;
556 div_off = clk->rate_offset;
558 switch ((*div_sel & SRC_RATE_SEL_MASK)) {
560 div_addr = (u32)&CM_CLKSEL_MPU;
564 div_addr = (u32)&CM_CLKSEL_DSP;
565 if (cpu_is_omap2420()) {
566 if ((div_off == 0) || (div_off == 8))
568 else if (div_off == 5)
570 } else if (cpu_is_omap2430()) {
573 else if (div_off == 5)
578 div_addr = (u32)&CM_CLKSEL_GFX;
583 div_addr = (u32)&CM_CLKSEL_MDM;
587 case CM_SYSCLKOUT_SEL1:
588 div_addr = (u32)&PRCM_CLKOUT_CTRL;
589 if ((div_off == 3) || (div_off = 11))
593 div_addr = (u32)&CM_CLKSEL1_CORE;
597 case 15: /* vylnc-2420 */
611 if (unlikely(mask == ~0))
616 if (unlikely(div_addr == 0))
620 reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
622 /* Normalize back to divider value */
629 * Return divider to be applied to parent clock.
632 static u32 omap2_clksel_get_divisor(struct clk *clk)
635 u32 div, div_sel, div_off, field_mask, field_val;
637 /* isolate control register */
638 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
640 div_off = clk->rate_offset;
641 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
645 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
646 div = omap2_clksel_to_divisor(div_sel, field_val);
651 /* Set the clock rate for a clock source */
652 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
657 u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
660 if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
662 return omap2_reprogram_dpll(clk, rate);
664 /* Isolate control register */
665 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
666 div_off = clk->rate_offset;
668 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
669 if (validrate != rate)
672 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
676 if (clk->flags & CM_SYSCLKOUT_SEL1) {
697 reg = (void __iomem *)div_sel;
699 reg_val = __raw_readl(reg);
700 reg_val &= ~(field_mask << div_off);
701 reg_val |= (field_val << div_off);
702 __raw_writel(reg_val, reg);
704 clk->rate = clk->parent->rate / field_val;
706 if (clk->flags & DELAYED_APP) {
707 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
711 } else if (clk->set_rate != 0)
712 ret = clk->set_rate(clk, rate);
714 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
720 /* Converts encoded control register address into a full address */
721 static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
722 struct clk *src_clk, u32 *field_mask)
724 u32 val = ~0, src_reg_addr = 0, mask = 0;
726 /* Find target control register.*/
727 switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
729 src_reg_addr = (u32)&CM_CLKSEL1_CORE;
730 if (reg_offset == 13) { /* DSS2_fclk */
732 if (src_clk == &sys_ck)
734 if (src_clk == &func_48m_ck)
736 } else if (reg_offset == 8) { /* DSS1_fclk */
738 if (src_clk == &sys_ck)
740 else if (src_clk == &core_ck) /* divided clock */
741 val = 0x10; /* rate needs fixing */
742 } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
744 if(src_clk == &func_96m_ck)
746 else if (src_clk == &core_ck)
751 src_reg_addr = (u32)&CM_CLKSEL2_CORE;
753 if (src_clk == &func_32k_ck)
755 if (src_clk == &sys_ck)
757 if (src_clk == &alt_ck)
761 src_reg_addr = (u32)&CM_CLKSEL_WKUP;
763 if (src_clk == &func_32k_ck)
765 if (src_clk == &sys_ck)
767 if (src_clk == &alt_ck)
771 src_reg_addr = (u32)&CM_CLKSEL1_PLL;
773 if (reg_offset == 0x3) {
774 if (src_clk == &apll96_ck)
776 if (src_clk == &alt_ck)
779 else if (reg_offset == 0x5) {
780 if (src_clk == &apll54_ck)
782 if (src_clk == &alt_ck)
787 src_reg_addr = (u32)&CM_CLKSEL2_PLL;
789 if (src_clk == &func_32k_ck)
791 if (src_clk == &dpll_ck)
794 case CM_SYSCLKOUT_SEL1:
795 src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
797 if (src_clk == &dpll_ck)
799 if (src_clk == &sys_ck)
801 if (src_clk == &func_96m_ck)
803 if (src_clk == &func_54m_ck)
808 if (val == ~0) /* Catch errors in offset */
811 *type_to_addr = src_reg_addr;
817 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
820 u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
823 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
826 if (clk->flags & SRC_SEL_MASK) { /* On-chip SEL collection */
827 src_sel = (SRC_RATE_SEL_MASK & clk->flags);
828 src_off = clk->src_offset;
831 goto set_parent_error;
833 field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
836 reg = (void __iomem *)src_sel;
838 if (clk->usecount > 0)
839 _omap2_clk_disable(clk);
841 /* Set new source value (previous dividers if any in effect) */
842 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
843 reg_val |= (field_val << src_off);
844 __raw_writel(reg_val, reg);
847 if (clk->flags & DELAYED_APP) {
848 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
851 if (clk->usecount > 0)
852 _omap2_clk_enable(clk);
854 clk->parent = new_parent;
856 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
857 if ((new_parent == &core_ck) && (clk == &dss1_fck))
858 clk->rate = new_parent->rate / 0x10;
860 clk->rate = new_parent->rate;
862 if (unlikely(clk->flags & RATE_PROPAGATES))
867 clk->parent = new_parent;
868 rate = new_parent->rate;
869 omap2_clk_set_rate(clk, rate);
877 /* Sets basic clocks based on the specified rate */
878 static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
880 u32 flags, cur_rate, done_rate, bypass = 0;
882 struct prcm_config *prcm;
883 unsigned long found_speed = 0;
885 if (clk != &virt_prcm_set)
888 /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */
889 if (cpu_is_omap2420())
890 cpu_mask = RATE_IN_242X;
891 else if (cpu_is_omap2430())
892 cpu_mask = RATE_IN_243X;
894 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
895 if (!(prcm->flags & cpu_mask))
898 if (prcm->xtal_speed != sys_ck.rate)
901 if (prcm->mpu_speed <= rate) {
902 found_speed = prcm->mpu_speed;
908 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
913 curr_prcm_set = prcm;
914 cur_rate = omap2_get_dpll_rate(&dpll_ck);
916 if (prcm->dpll_speed == cur_rate / 2) {
917 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
918 } else if (prcm->dpll_speed == cur_rate * 2) {
919 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
920 } else if (prcm->dpll_speed != cur_rate) {
921 local_irq_save(flags);
923 if (prcm->dpll_speed == prcm->xtal_speed)
926 if ((prcm->cm_clksel2_pll & 0x3) == 2)
927 done_rate = PRCM_FULL_SPEED;
929 done_rate = PRCM_HALF_SPEED;
932 CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
934 /* dsp + iva1 div(2420), iva2.1(2430) */
935 CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
937 CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
939 /* Major subsystem dividers */
940 CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
941 if (cpu_is_omap2430())
942 CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
944 /* x2 to enter init_mem */
945 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
947 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
950 omap2_init_memory_params(omap2_dll_force_needed());
951 omap2_reprogram_sdrc(done_rate, 0);
953 local_irq_restore(flags);
955 omap2_clksel_recalc(&dpll_ck);
960 /*-------------------------------------------------------------------------
961 * Omap2 clock reset and init functions
962 *-------------------------------------------------------------------------*/
964 #ifdef CONFIG_OMAP_RESET_CLOCKS
965 static void __init omap2_clk_disable_unused(struct clk *clk)
969 regval32 = __raw_readl(clk->enable_reg);
970 if ((regval32 & (1 << clk->enable_bit)) == 0)
973 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
974 _omap2_clk_disable(clk);
977 #define omap2_clk_disable_unused NULL
980 static struct clk_functions omap2_clk_functions = {
981 .clk_enable = omap2_clk_enable,
982 .clk_disable = omap2_clk_disable,
983 .clk_round_rate = omap2_clk_round_rate,
984 .clk_set_rate = omap2_clk_set_rate,
985 .clk_set_parent = omap2_clk_set_parent,
986 .clk_disable_unused = omap2_clk_disable_unused,
989 static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
991 u32 div, aplls, sclk = 13000000;
993 aplls = CM_CLKSEL1_PLL;
994 aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
995 aplls >>= 23; /* Isolate field, 0,2,3 */
1001 else if (aplls == 3)
1004 div = PRCM_CLKSRC_CTRL;
1005 div &= ((1 << 7) | (1 << 6));
1006 div >>= sys->rate_offset;
1008 osc->rate = sclk * div;
1013 * Set clocks for bypass mode for reboot to work.
1015 void omap2_clk_prepare_for_reboot(void)
1019 if (vclk == NULL || sclk == NULL)
1022 rate = clk_get_rate(sclk);
1023 clk_set_rate(vclk, rate);
1027 * Switch the MPU rate if specified on cmdline.
1028 * We cannot do this early until cmdline is parsed.
1030 static int __init omap2_clk_arch_init(void)
1035 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
1036 printk(KERN_ERR "Could not find matching MPU rate\n");
1038 propagate_rate(&osc_ck); /* update main root fast */
1039 propagate_rate(&func_32k_ck); /* update main root slow */
1041 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
1042 "%ld.%01ld/%ld/%ld MHz\n",
1043 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1044 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1048 arch_initcall(omap2_clk_arch_init);
1050 int __init omap2_clk_init(void)
1052 struct prcm_config *prcm;
1056 clk_init(&omap2_clk_functions);
1057 omap2_get_crystal_rate(&osc_ck, &sys_ck);
1059 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
1062 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
1063 clk_register(*clkp);
1067 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
1068 clk_register(*clkp);
1073 /* Check the MPU rate set by bootloader */
1074 clkrate = omap2_get_dpll_rate(&dpll_ck);
1075 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1076 if (prcm->xtal_speed != sys_ck.rate)
1078 if (prcm->dpll_speed <= clkrate)
1081 curr_prcm_set = prcm;
1083 propagate_rate(&osc_ck); /* update main root fast */
1084 propagate_rate(&func_32k_ck); /* update main root slow */
1086 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
1087 "%ld.%01ld/%ld/%ld MHz\n",
1088 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1089 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1092 * Only enable those clocks we will need, let the drivers
1093 * enable other clocks as necessary
1095 clk_enable(&sync_32k_ick);
1096 clk_enable(&omapctrl_ick);
1097 if (cpu_is_omap2430())
1098 clk_enable(&sdrc_ick);
1100 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1101 vclk = clk_get(NULL, "virt_prcm_set");
1102 sclk = clk_get(NULL, "sys_ck");