arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  *  Copyright (C) 2007 Texas Instruments, Inc.
  13  *  Copyright (C) 2007 Nokia Corporation
  14  *  Paul Walmsley
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  22 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  23
  24 #include "prm.h"
  25 #include "cm.h"
  26 #include "prm_regbits_24xx.h"
  27 #include "cm_regbits_24xx.h"
  28
  29 static void omap2_sys_clk_recalc(struct clk * clk);
  30 static void omap2_clksel_recalc(struct clk * clk);
  31 static void omap2_table_mpu_recalc(struct clk *clk);
  32 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  33 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  34 static void omap2_clk_disable(struct clk *clk);
  35 static void omap2_sys_clk_recalc(struct clk * clk);
  36 static void omap2_init_clksel_parent(struct clk *clk);
  37 static u32 omap2_clksel_get_divisor(struct clk *clk);
  38 static u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
  39 static u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
  40 static void omap2_dpll_recalc(struct clk *clk);
  41 static void omap2_fixed_divisor_recalc(struct clk *clk);
  42 static long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
  43 static int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
  44 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
  45
  46 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  47  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  48  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  49  */
  50 struct prcm_config {
  51         unsigned long xtal_speed;       /* crystal rate */
  52         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  53         unsigned long mpu_speed;        /* speed of MPU */
  54         unsigned long cm_clksel_mpu;    /* mpu divider */
  55         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  56         unsigned long cm_clksel_gfx;    /* gfx dividers */
  57         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  58         unsigned long cm_clksel1_pll;   /* m,n */
  59         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  60         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  61         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  62         unsigned char flags;
  63 };
  64
  65 /*
  66  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  67  * These configurations are characterized by voltage and speed for clocks.
  68  * The device is only validated for certain combinations. One way to express
  69  * these combinations is via the 'ratio's' which the clocks operate with
  70  * respect to each other. These ratio sets are for a given voltage/DPLL
  71  * setting. All configurations can be described by a DPLL setting and a ratio
  72  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  73  *
  74  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  75  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  76  * 2430 (iva2.1, NOdsp, mdm)
  77  */
  78
  79 /* Core fields for cm_clksel, not ratio governed */
  80 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  81 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  82 #define RX_CLKSEL_SSI                   (0x5 << 20)
  83
  84 /*-------------------------------------------------------------------------
  85  * Voltage/DPLL ratios
  86  *-------------------------------------------------------------------------*/
  87
  88 /* 2430 Ratio's, 2430-Ratio Config 1 */
  89 #define R1_CLKSEL_L3                    (4 << 0)
  90 #define R1_CLKSEL_L4                    (2 << 5)
  91 #define R1_CLKSEL_USB                   (4 << 25)
  92 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  93                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  94                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  95 #define R1_CLKSEL_MPU                   (2 << 0)
  96 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  97 #define R1_CLKSEL_DSP                   (2 << 0)
  98 #define R1_CLKSEL_DSP_IF                (2 << 5)
  99 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 100 #define R1_CLKSEL_GFX                   (2 << 0)
 101 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 102 #define R1_CLKSEL_MDM                   (4 << 0)
 103 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 104
 105 /* 2430-Ratio Config 2 */
 106 #define R2_CLKSEL_L3                    (6 << 0)
 107 #define R2_CLKSEL_L4                    (2 << 5)
 108 #define R2_CLKSEL_USB                   (2 << 25)
 109 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 110                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 111                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 112 #define R2_CLKSEL_MPU                   (2 << 0)
 113 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 114 #define R2_CLKSEL_DSP                   (2 << 0)
 115 #define R2_CLKSEL_DSP_IF                (3 << 5)
 116 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 117 #define R2_CLKSEL_GFX                   (2 << 0)
 118 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 119 #define R2_CLKSEL_MDM                   (6 << 0)
 120 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 121
 122 /* 2430-Ratio Bootm (BYPASS) */
 123 #define RB_CLKSEL_L3                    (1 << 0)
 124 #define RB_CLKSEL_L4                    (1 << 5)
 125 #define RB_CLKSEL_USB                   (1 << 25)
 126 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 127                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 128                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 129 #define RB_CLKSEL_MPU                   (1 << 0)
 130 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 131 #define RB_CLKSEL_DSP                   (1 << 0)
 132 #define RB_CLKSEL_DSP_IF                (1 << 5)
 133 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 134 #define RB_CLKSEL_GFX                   (1 << 0)
 135 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 136 #define RB_CLKSEL_MDM                   (1 << 0)
 137 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 138
 139 /* 2420 Ratio Equivalents */
 140 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 141 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 142
 143 /* 2420-PRCM III 532MHz core */
 144 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 145 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 146 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 147 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 148                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 149                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 150                                         RIII_CLKSEL_L3
 151 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 152 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 153 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 154 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 155 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 156 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 157 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 158 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 159                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 160                                         RIII_CLKSEL_DSP
 161 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 162 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 163
 164 /* 2420-PRCM II 600MHz core */
 165 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 166 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 167 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 168 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 169                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 170                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 171                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 172 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 173 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 174 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 175 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 176 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 177 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 178 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 179 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 180                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 181                                         RII_CLKSEL_DSP
 182 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 183 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 184
 185 /* 2420-PRCM I 660MHz core */
 186 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 187 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 188 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 189 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 190                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 191                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 192                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 193 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 194 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 195 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 196 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 197 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 198 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 199 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 200 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 201                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 202                                         RI_CLKSEL_DSP
 203 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 204 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 205
 206 /* 2420-PRCM VII (boot) */
 207 #define RVII_CLKSEL_L3                  (1 << 0)
 208 #define RVII_CLKSEL_L4                  (1 << 5)
 209 #define RVII_CLKSEL_DSS1                (1 << 8)
 210 #define RVII_CLKSEL_DSS2                (0 << 13)
 211 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 212 #define RVII_CLKSEL_SSI                 (1 << 20)
 213 #define RVII_CLKSEL_USB                 (1 << 25)
 214
 215 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 216                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 217                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 218
 219 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 220 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 221
 222 #define RVII_CLKSEL_DSP                 (1 << 0)
 223 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 224 #define RVII_SYNC_DSP                   (0 << 7)
 225 #define RVII_CLKSEL_IVA                 (1 << 8)
 226 #define RVII_SYNC_IVA                   (0 << 13)
 227 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 228                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 229
 230 #define RVII_CLKSEL_GFX                 (1 << 0)
 231 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 232
 233 /*-------------------------------------------------------------------------
 234  * 2430 Target modes: Along with each configuration the CPU has several
 235  * modes which goes along with them. Modes mainly are the addition of
 236  * describe DPLL combinations to go along with a ratio.
 237  *-------------------------------------------------------------------------*/
 238
 239 /* Hardware governed */
 240 #define MX_48M_SRC                      (0 << 3)
 241 #define MX_54M_SRC                      (0 << 5)
 242 #define MX_APLLS_CLIKIN_12              (3 << 23)
 243 #define MX_APLLS_CLIKIN_13              (2 << 23)
 244 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 245
 246 /*
 247  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 248  * #2   (ratio1) baseport-target
 249  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 250  */
 251 #define M5A_DPLL_MULT_12                (133 << 12)
 252 #define M5A_DPLL_DIV_12                 (5 << 8)
 253 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 254                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 255                                         MX_APLLS_CLIKIN_12
 256 #define M5A_DPLL_MULT_13                (266 << 12)
 257 #define M5A_DPLL_DIV_13                 (12 << 8)
 258 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 259                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 260                                         MX_APLLS_CLIKIN_13
 261 #define M5A_DPLL_MULT_19                (180 << 12)
 262 #define M5A_DPLL_DIV_19                 (12 << 8)
 263 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 264                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 265                                         MX_APLLS_CLIKIN_19_2
 266 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 267 #define M5B_DPLL_MULT_12                (50 << 12)
 268 #define M5B_DPLL_DIV_12                 (2 << 8)
 269 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 270                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 271                                         MX_APLLS_CLIKIN_12
 272 #define M5B_DPLL_MULT_13                (200 << 12)
 273 #define M5B_DPLL_DIV_13                 (12 << 8)
 274
 275 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 276                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 277                                         MX_APLLS_CLIKIN_13
 278 #define M5B_DPLL_MULT_19                (125 << 12)
 279 #define M5B_DPLL_DIV_19                 (31 << 8)
 280 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 281                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 282                                         MX_APLLS_CLIKIN_19_2
 283 /*
 284  * #4   (ratio2)
 285  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 286  */
 287 #define M3_DPLL_MULT_12                 (55 << 12)
 288 #define M3_DPLL_DIV_12                  (1 << 8)
 289 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 290                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 291                                         MX_APLLS_CLIKIN_12
 292 #define M3_DPLL_MULT_13                 (330 << 12)
 293 #define M3_DPLL_DIV_13                  (12 << 8)
 294 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 295                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 296                                         MX_APLLS_CLIKIN_13
 297 #define M3_DPLL_MULT_19                 (275 << 12)
 298 #define M3_DPLL_DIV_19                  (15 << 8)
 299 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 300                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 301                                         MX_APLLS_CLIKIN_19_2
 302 /* boot (boot) */
 303 #define MB_DPLL_MULT                    (1 << 12)
 304 #define MB_DPLL_DIV                     (0 << 8)
 305 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 306                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 307
 308 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 309                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 310
 311 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 312                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 313
 314 /*
 315  * 2430 - chassis (sedna)
 316  * 165 (ratio1) same as above #2
 317  * 150 (ratio1)
 318  * 133 (ratio2) same as above #4
 319  * 110 (ratio2) same as above #3
 320  * 104 (ratio2)
 321  * boot (boot)
 322  */
 323
 324 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 325 #define MI_DPLL_MULT_12                 (55 << 12)
 326 #define MI_DPLL_DIV_12                  (1 << 8)
 327 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 328                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 329                                         MX_APLLS_CLIKIN_12
 330
 331 /*
 332  * 2420 Equivalent - mode registers
 333  * PRCM II , target DPLL = 2*300MHz = 600MHz
 334  */
 335 #define MII_DPLL_MULT_12                (50 << 12)
 336 #define MII_DPLL_DIV_12                 (1 << 8)
 337 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 338                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 339                                         MX_APLLS_CLIKIN_12
 340 #define MII_DPLL_MULT_13                (300 << 12)
 341 #define MII_DPLL_DIV_13                 (12 << 8)
 342 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 343                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 344                                         MX_APLLS_CLIKIN_13
 345
 346 /* PRCM III target DPLL = 2*266 = 532MHz*/
 347 #define MIII_DPLL_MULT_12               (133 << 12)
 348 #define MIII_DPLL_DIV_12                (5 << 8)
 349 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 350                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 351                                         MX_APLLS_CLIKIN_12
 352 #define MIII_DPLL_MULT_13               (266 << 12)
 353 #define MIII_DPLL_DIV_13                (12 << 8)
 354 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 355                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 356                                         MX_APLLS_CLIKIN_13
 357
 358 /* PRCM VII (boot bypass) */
 359 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 360 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 361
 362 /* High and low operation value */
 363 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 364 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 365
 366 /*
 367  * These represent optimal values for common parts, it won't work for all.
 368  * As long as you scale down, most parameters are still work, they just
 369  * become sub-optimal. The RFR value goes in the opposite direction. If you
 370  * don't adjust it down as your clock period increases the refresh interval
 371  * will not be met. Setting all parameters for complete worst case may work,
 372  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 373  * unlocked and their value needs run time calibration. A dynamic call is
 374  * need for that as no single right value exists acorss production samples.
 375  *
 376  * Only the FULL speed values are given. Current code is such that rate
 377  * changes must be made at DPLLoutx2. The actual value adjustment for low
 378  * frequency operation will be handled by omap_set_performance()
 379  *
 380  * By having the boot loader boot up in the fastest L4 speed available likely
 381  * will result in something which you can switch between.
 382  */
 383 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 384 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 385 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 386 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 387 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 388
 389 /* MPU speed defines */
 390 #define S12M    12000000
 391 #define S13M    13000000
 392 #define S19M    19200000
 393 #define S26M    26000000
 394 #define S100M   100000000
 395 #define S133M   133000000
 396 #define S150M   150000000
 397 #define S165M   165000000
 398 #define S200M   200000000
 399 #define S266M   266000000
 400 #define S300M   300000000
 401 #define S330M   330000000
 402 #define S400M   400000000
 403 #define S532M   532000000
 404 #define S600M   600000000
 405 #define S660M   660000000
 406
 407 /*-------------------------------------------------------------------------
 408  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 409  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 410  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 411  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 412  *
 413  * Filling in table based on H4 boards and 2430-SDPs variants available.
 414  * There are quite a few more rates combinations which could be defined.
 415  *
 416  * When multiple values are defined the start up will try and choose the
 417  * fastest one. If a 'fast' value is defined, then automatically, the /2
 418  * one should be included as it can be used.    Generally having more that
 419  * one fast set does not make sense, as static timings need to be changed
 420  * to change the set.    The exception is the bypass setting which is
 421  * availble for low power bypass.
 422  *
 423  * Note: This table needs to be sorted, fastest to slowest.
 424  *-------------------------------------------------------------------------*/
 425 static struct prcm_config rate_table[] = {
 426         /* PRCM I - FAST */
 427         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 428                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 429                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 430                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 431                 RATE_IN_242X},
 432
 433         /* PRCM II - FAST */
 434         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 435                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 436                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 437                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 438                 RATE_IN_242X},
 439
 440         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 441                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 442                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 443                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 444                 RATE_IN_242X},
 445
 446         /* PRCM III - FAST */
 447         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 448                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 449                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 450                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 451                 RATE_IN_242X},
 452
 453         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 454                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 455                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 456                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 457                 RATE_IN_242X},
 458
 459         /* PRCM II - SLOW */
 460         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 461                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 462                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 463                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 464                 RATE_IN_242X},
 465
 466         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 467                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 468                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 469                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 470                 RATE_IN_242X},
 471
 472         /* PRCM III - SLOW */
 473         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 474                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 475                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 476                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 477                 RATE_IN_242X},
 478
 479         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 480                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 481                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 482                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 483                 RATE_IN_242X},
 484
 485         /* PRCM-VII (boot-bypass) */
 486         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 487                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 488                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 489                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 490                 RATE_IN_242X},
 491
 492         /* PRCM-VII (boot-bypass) */
 493         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 494                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 495                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 496                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 497                 RATE_IN_242X},
 498
 499         /* PRCM #3 - ratio2 (ES2) - FAST */
 500         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 501                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 502                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 504                 V24XX_SDRC_RFR_CTRL_110MHz,
 505                 RATE_IN_243X},
 506
 507         /* PRCM #5a - ratio1 - FAST */
 508         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 509                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 510                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 511                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 512                 V24XX_SDRC_RFR_CTRL_133MHz,
 513                 RATE_IN_243X},
 514
 515         /* PRCM #5b - ratio1 - FAST */
 516         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 517                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 518                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 519                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 520                 V24XX_SDRC_RFR_CTRL_100MHz,
 521                 RATE_IN_243X},
 522
 523         /* PRCM #3 - ratio2 (ES2) - SLOW */
 524         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 525                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 526                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 527                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 528                 V24XX_SDRC_RFR_CTRL_110MHz,
 529                 RATE_IN_243X},
 530
 531         /* PRCM #5a - ratio1 - SLOW */
 532         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 533                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 534                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 535                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 536                 V24XX_SDRC_RFR_CTRL_133MHz,
 537                 RATE_IN_243X},
 538
 539         /* PRCM #5b - ratio1 - SLOW*/
 540         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 541                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 542                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 543                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 544                 V24XX_SDRC_RFR_CTRL_100MHz,
 545                 RATE_IN_243X},
 546
 547         /* PRCM-boot/bypass */
 548         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 549                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 550                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 551                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 552                 V24XX_SDRC_RFR_CTRL_BYPASS,
 553                 RATE_IN_243X},
 554
 555         /* PRCM-boot/bypass */
 556         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 557                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 558                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 559                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 560                 V24XX_SDRC_RFR_CTRL_BYPASS,
 561                 RATE_IN_243X},
 562
 563         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 564 };
 565
 566 /*-------------------------------------------------------------------------
 567  * 24xx clock tree.
 568  *
 569  * NOTE:In many cases here we are assigning a 'default' parent. In many
 570  *      cases the parent is selectable. The get/set parent calls will also
 571  *      switch sources.
 572  *
 573  *      Many some clocks say always_enabled, but they can be auto idled for
 574  *      power savings. They will always be available upon clock request.
 575  *
 576  *      Several sources are given initial rates which may be wrong, this will
 577  *      be fixed up in the init func.
 578  *
 579  *      Things are broadly separated below by clock domains. It is
 580  *      noteworthy that most periferals have dependencies on multiple clock
 581  *      domains. Many get their interface clocks from the L4 domain, but get
 582  *      functional clocks from fixed sources or other core domain derived
 583  *      clocks.
 584  *-------------------------------------------------------------------------*/
 585
 586 /* Base external input clocks */
 587 static struct clk func_32k_ck = {
 588         .name           = "func_32k_ck",
 589         .rate           = 32000,
 590         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 591                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 592         .recalc         = &propagate_rate,
 593 };
 594
 595 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 596 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 597         .name           = "osc_ck",
 598         .rate           = 26000000,             /* fixed up in clock init */
 599         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 600                                 RATE_FIXED | RATE_PROPAGATES,
 601         .recalc         = &propagate_rate,
 602 };
 603
 604 /* With out modem likely 12MHz, with modem likely 13MHz */
 605 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 606         .name           = "sys_ck",             /* ~ ref_clk also */
 607         .parent         = &osc_ck,
 608         .rate           = 13000000,
 609         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 610                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 611         .recalc         = &omap2_sys_clk_recalc,
 612 };
 613
 614 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 615         .name           = "alt_ck",
 616         .rate           = 54000000,
 617         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 618                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 619         .recalc         = &propagate_rate,
 620 };
 621
 622 /*
 623  * Analog domain root source clocks
 624  */
 625
 626 /* dpll_ck, is broken out in to special cases through clksel */
 627 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 628  * deal with this
 629  */
 630 static struct clk dpll_ck = {
 631         .name           = "dpll_ck",
 632         .parent         = &sys_ck,              /* Can be func_32k also */
 633         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 634                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 635         .recalc         = &omap2_dpll_recalc,
 636         .set_rate       = &omap2_reprogram_dpll,
 637 };
 638
 639 static struct clk apll96_ck = {
 640         .name           = "apll96_ck",
 641         .parent         = &sys_ck,
 642         .rate           = 96000000,
 643         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 644                                 RATE_FIXED | RATE_PROPAGATES,
 645         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 646         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 647         .recalc         = &propagate_rate,
 648 };
 649
 650 static struct clk apll54_ck = {
 651         .name           = "apll54_ck",
 652         .parent         = &sys_ck,
 653         .rate           = 54000000,
 654         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 655                                 RATE_FIXED | RATE_PROPAGATES,
 656         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 657         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 658         .recalc         = &propagate_rate,
 659 };
 660
 661 /*
 662  * PRCM digital base sources
 663  */
 664
 665 /* func_54m_ck */
 666
 667 static const struct clksel_rate func_54m_apll54_rates[] = {
 668         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 669         { .div = 0 },
 670 };
 671
 672 static const struct clksel_rate func_54m_alt_rates[] = {
 673         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 674         { .div = 0 },
 675 };
 676
 677 static const struct clksel func_54m_clksel[] = {
 678         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 679         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 680         { .parent = NULL },
 681 };
 682
 683 static struct clk func_54m_ck = {
 684         .name           = "func_54m_ck",
 685         .parent         = &apll54_ck,   /* can also be alt_clk */
 686         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 687                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 688         .init           = &omap2_init_clksel_parent,
 689         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 690         .clksel_mask    = OMAP24XX_54M_SOURCE,
 691         .clksel         = func_54m_clksel,
 692         .recalc         = &omap2_clksel_recalc,
 693 };
 694
 695 static struct clk core_ck = {
 696         .name           = "core_ck",
 697         .parent         = &dpll_ck,             /* can also be 32k */
 698         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 699                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 700         .recalc         = &followparent_recalc,
 701 };
 702
 703 /* func_96m_ck */
 704 static const struct clksel_rate func_96m_apll96_rates[] = {
 705         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 706         { .div = 0 },
 707 };
 708
 709 static const struct clksel_rate func_96m_alt_rates[] = {
 710         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 711         { .div = 0 },
 712 };
 713
 714 static const struct clksel func_96m_clksel[] = {
 715         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 716         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 717         { .parent = NULL }
 718 };
 719
 720 /* The parent of this clock is not selectable on 2420. */
 721 static struct clk func_96m_ck = {
 722         .name           = "func_96m_ck",
 723         .parent         = &apll96_ck,
 724         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 725                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 726         .init           = &omap2_init_clksel_parent,
 727         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 728         .clksel_mask    = OMAP2430_96M_SOURCE,
 729         .clksel         = func_96m_clksel,
 730         .recalc         = &omap2_clksel_recalc,
 731         .round_rate     = &omap2_clksel_round_rate,
 732         .set_rate       = &omap2_clksel_set_rate
 733 };
 734
 735 /* func_48m_ck */
 736
 737 static const struct clksel_rate func_48m_apll96_rates[] = {
 738         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 739         { .div = 0 },
 740 };
 741
 742 static const struct clksel_rate func_48m_alt_rates[] = {
 743         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 744         { .div = 0 },
 745 };
 746
 747 static const struct clksel func_48m_clksel[] = {
 748         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 749         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 750         { .parent = NULL }
 751 };
 752
 753 static struct clk func_48m_ck = {
 754         .name           = "func_48m_ck",
 755         .parent         = &apll96_ck,    /* 96M or Alt */
 756         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 757                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 758         .init           = &omap2_init_clksel_parent,
 759         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 760         .clksel_mask    = OMAP24XX_48M_SOURCE,
 761         .clksel         = func_48m_clksel,
 762         .recalc         = &omap2_clksel_recalc,
 763         .round_rate     = &omap2_clksel_round_rate,
 764         .set_rate       = &omap2_clksel_set_rate
 765 };
 766
 767 static struct clk func_12m_ck = {
 768         .name           = "func_12m_ck",
 769         .parent         = &func_48m_ck,
 770         .fixed_div      = 4,
 771         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 772                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 773         .recalc         = &omap2_fixed_divisor_recalc,
 774 };
 775
 776 /* Secure timer, only available in secure mode */
 777 static struct clk wdt1_osc_ck = {
 778         .name           = "ck_wdt1_osc",
 779         .parent         = &osc_ck,
 780         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 781         .recalc         = &followparent_recalc,
 782 };
 783
 784 /*
 785  * The common_clkout* clksel_rate structs are common to
 786  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 787  * sys_clkout2_* are 2420-only, so the
 788  * clksel_rate flags fields are inaccurate for those clocks. This is
 789  * harmless since access to those clocks are gated by the struct clk
 790  * flags fields, which mark them as 2420-only.
 791  */
 792 static const struct clksel_rate common_clkout_src_core_rates[] = {
 793         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 794         { .div = 0 }
 795 };
 796
 797 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 798         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 799         { .div = 0 }
 800 };
 801
 802 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 803         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 804         { .div = 0 }
 805 };
 806
 807 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 808         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 809         { .div = 0 }
 810 };
 811
 812 static const struct clksel common_clkout_src_clksel[] = {
 813         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 814         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 815         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 816         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 817         { .parent = NULL }
 818 };
 819
 820 static struct clk sys_clkout_src = {
 821         .name           = "sys_clkout_src",
 822         .parent         = &func_54m_ck,
 823         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 824                                 RATE_PROPAGATES,
 825         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 826         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 827         .init           = &omap2_init_clksel_parent,
 828         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 829         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 830         .clksel         = common_clkout_src_clksel,
 831         .recalc         = &omap2_clksel_recalc,
 832         .round_rate     = &omap2_clksel_round_rate,
 833         .set_rate       = &omap2_clksel_set_rate
 834 };
 835
 836 static const struct clksel_rate common_clkout_rates[] = {
 837         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 838         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 839         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 840         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 841         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 842         { .div = 0 },
 843 };
 844
 845 static const struct clksel sys_clkout_clksel[] = {
 846         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 847         { .parent = NULL }
 848 };
 849
 850 static struct clk sys_clkout = {
 851         .name           = "sys_clkout",
 852         .parent         = &sys_clkout_src,
 853         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 854                                 PARENT_CONTROLS_CLOCK,
 855         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 856         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 857         .clksel         = sys_clkout_clksel,
 858         .recalc         = &omap2_clksel_recalc,
 859         .round_rate     = &omap2_clksel_round_rate,
 860         .set_rate       = &omap2_clksel_set_rate
 861 };
 862
 863 /* In 2430, new in 2420 ES2 */
 864 static struct clk sys_clkout2_src = {
 865         .name           = "sys_clkout2_src",
 866         .parent         = &func_54m_ck,
 867         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 868         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 869         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 870         .init           = &omap2_init_clksel_parent,
 871         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 872         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 873         .clksel         = common_clkout_src_clksel,
 874         .recalc         = &omap2_clksel_recalc,
 875         .round_rate     = &omap2_clksel_round_rate,
 876         .set_rate       = &omap2_clksel_set_rate
 877 };
 878
 879 static const struct clksel sys_clkout2_clksel[] = {
 880         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 881         { .parent = NULL }
 882 };
 883
 884 /* In 2430, new in 2420 ES2 */
 885 static struct clk sys_clkout2 = {
 886         .name           = "sys_clkout2",
 887         .parent         = &sys_clkout2_src,
 888         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 889         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 890         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 891         .clksel         = sys_clkout2_clksel,
 892         .recalc         = &omap2_clksel_recalc,
 893         .round_rate     = &omap2_clksel_round_rate,
 894         .set_rate       = &omap2_clksel_set_rate
 895 };
 896
 897 static struct clk emul_ck = {
 898         .name           = "emul_ck",
 899         .parent         = &func_54m_ck,
 900         .flags          = CLOCK_IN_OMAP242X,
 901         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 902         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 903         .recalc         = &followparent_recalc,
 904
 905 };
 906
 907 /*
 908  * MPU clock domain
 909  *      Clocks:
 910  *              MPU_FCLK, MPU_ICLK
 911  *              INT_M_FCLK, INT_M_I_CLK
 912  *
 913  * - Individual clocks are hardware managed.
 914  * - Base divider comes from: CM_CLKSEL_MPU
 915  *
 916  */
 917 static const struct clksel_rate mpu_core_rates[] = {
 918         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 919         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 920         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 921         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 922         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 923         { .div = 0 },
 924 };
 925
 926 static const struct clksel mpu_clksel[] = {
 927         { .parent = &core_ck, .rates = mpu_core_rates },
 928         { .parent = NULL }
 929 };
 930
 931 static struct clk mpu_ck = {    /* Control cpu */
 932         .name           = "mpu_ck",
 933         .parent         = &core_ck,
 934         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 935                                 ALWAYS_ENABLED | DELAYED_APP |
 936                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 937         .init           = &omap2_init_clksel_parent,
 938         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 939         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 940         .clksel         = mpu_clksel,
 941         .recalc         = &omap2_clksel_recalc,
 942         .round_rate     = &omap2_clksel_round_rate,
 943         .set_rate       = &omap2_clksel_set_rate
 944 };
 945
 946 /*
 947  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 948  * Clocks:
 949  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 950  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 951  */
 952 /* XXX Okay, this is dumb.  iva2_1fck and dsp_fck are the same clock.
 953  * they should just be treated as such.
 954  */
 955
 956 /* iva2_1_fck */
 957 static const struct clksel_rate iva2_1_fck_core_rates[] = {
 958         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 959         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 960         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 961         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 962         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 963         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 964         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 965         { .div = 0 },
 966 };
 967
 968 static const struct clksel iva2_1_fck_clksel[] = {
 969         { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
 970         { .parent = NULL }
 971 };
 972
 973 static struct clk iva2_1_fck = {
 974         .name           = "iva2_1_fck",
 975         .parent         = &core_ck,
 976         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES |
 977                                 CONFIG_PARTICIPANT,
 978         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 979         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 980         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 981         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 982         .clksel         = iva2_1_fck_clksel,
 983         .recalc         = &omap2_clksel_recalc,
 984         .round_rate     = &omap2_clksel_round_rate,
 985         .set_rate       = &omap2_clksel_set_rate
 986 };
 987
 988 /* iva2_1_ick */
 989 static const struct clksel_rate iva2_1_ick_core_rates[] = {
 990         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 991         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 992         { .div = 3, .val = 3, .flags = RATE_IN_243X },
 993         { .div = 0 },
 994 };
 995
 996 static const struct clksel iva2_1_ick_clksel[] = {
 997         { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
 998         { .parent = NULL }
 999 };
1000
1001 static struct clk iva2_1_ick = {
1002         .name           = "iva2_1_ick",
1003         .parent         = &iva2_1_fck,
1004         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1005         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1006         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1007         .clksel         = iva2_1_ick_clksel,
1008         .recalc         = &omap2_clksel_recalc,
1009         .round_rate     = &omap2_clksel_round_rate,
1010         .set_rate       = &omap2_clksel_set_rate
1011 };
1012
1013 /*
1014  * Won't be too specific here. The core clock comes into this block
1015  * it is divided then tee'ed. One branch goes directly to xyz enable
1016  * controls. The other branch gets further divided by 2 then possibly
1017  * routed into a synchronizer and out of clocks abc.
1018  */
1019 static const struct clksel_rate dsp_fck_core_rates[] = {
1020         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1021         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1022         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1023         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1024         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1025         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1026         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1027         { .div = 0 },
1028 };
1029
1030 static const struct clksel dsp_fck_clksel[] = {
1031         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1032         { .parent = NULL }
1033 };
1034
1035 static struct clk dsp_fck = {
1036         .name           = "dsp_fck",
1037         .parent         = &core_ck,
1038         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP |
1039                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1040         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1041         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1042         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1043         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1044         .clksel         = dsp_fck_clksel,
1045         .recalc         = &omap2_clksel_recalc,
1046         .round_rate     = &omap2_clksel_round_rate,
1047         .set_rate       = &omap2_clksel_set_rate
1048 };
1049
1050 static const struct clksel_rate dsp_ick_core_rates[] = {
1051         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1052         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1053         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1054         { .div = 0 },
1055 };
1056
1057 static const struct clksel dsp_ick_clksel[] = {
1058         { .parent = &core_ck, .rates = dsp_ick_core_rates },
1059         { .parent = NULL }
1060 };
1061
1062 static struct clk dsp_ick = {
1063         .name           = "dsp_ick",     /* apparently ipi and isp */
1064         .parent         = &core_ck,
1065         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1066         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1067         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
1068         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1069         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1070         .clksel         = dsp_ick_clksel,
1071         .recalc         = &omap2_clksel_recalc,
1072 };
1073
1074 static const struct clksel_rate iva1_ifck_core_rates[] = {
1075         { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1076         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1077         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1078         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1079         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1080         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1081         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1082         { .div = 0 },
1083 };
1084
1085 static const struct clksel iva1_ifck_clksel[] = {
1086         { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1087         { .parent = NULL }
1088 };
1089
1090 static struct clk iva1_ifck = {
1091         .name           = "iva1_ifck",
1092         .parent         = &core_ck,
1093         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1094                                 RATE_PROPAGATES | DELAYED_APP,
1095         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1096         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1097         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1098         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1099         .clksel         = iva1_ifck_clksel,
1100         .recalc         = &omap2_clksel_recalc,
1101         .round_rate     = &omap2_clksel_round_rate,
1102         .set_rate       = &omap2_clksel_set_rate
1103 };
1104
1105 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1106 static struct clk iva1_mpu_int_ifck = {
1107         .name           = "iva1_mpu_int_ifck",
1108         .parent         = &iva1_ifck,
1109         .flags          = CLOCK_IN_OMAP242X,
1110         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1111         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1112         .fixed_div      = 2,
1113         .recalc         = &omap2_fixed_divisor_recalc,
1114 };
1115
1116 /*
1117  * L3 clock domain
1118  * L3 clocks are used for both interface and functional clocks to
1119  * multiple entities. Some of these clocks are completely managed
1120  * by hardware, and some others allow software control. Hardware
1121  * managed ones general are based on directly CLK_REQ signals and
1122  * various auto idle settings. The functional spec sets many of these
1123  * as 'tie-high' for their enables.
1124  *
1125  * I-CLOCKS:
1126  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1127  *      CAM, HS-USB.
1128  * F-CLOCK
1129  *      SSI.
1130  *
1131  * GPMC memories and SDRC have timing and clock sensitive registers which
1132  * may very well need notification when the clock changes. Currently for low
1133  * operating points, these are taken care of in sleep.S.
1134  */
1135 static const struct clksel_rate core_l3_core_rates[] = {
1136         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1137         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1138         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1139         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1140         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1141         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1142         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1143         { .div = 0 }
1144 };
1145
1146 static const struct clksel core_l3_clksel[] = {
1147         { .parent = &core_ck, .rates = core_l3_core_rates },
1148         { .parent = NULL }
1149 };
1150
1151 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1152         .name           = "core_l3_ck",
1153         .parent         = &core_ck,
1154         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1155                                 ALWAYS_ENABLED | DELAYED_APP |
1156                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1157         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1158         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1159         .clksel         = core_l3_clksel,
1160         .recalc         = &omap2_clksel_recalc,
1161         .round_rate     = &omap2_clksel_round_rate,
1162         .set_rate       = &omap2_clksel_set_rate
1163 };
1164
1165 /* usb_l4_ick */
1166 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1167         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1168         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1169         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1170         { .div = 0 }
1171 };
1172
1173 static const struct clksel usb_l4_ick_clksel[] = {
1174         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1175         { .parent = NULL },
1176 };
1177
1178 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1179         .name           = "usb_l4_ick",
1180         .parent         = &core_l3_ck,
1181         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1182                                 DELAYED_APP | CONFIG_PARTICIPANT,
1183         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1184         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1185         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1186         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1187         .clksel         = usb_l4_ick_clksel,
1188         .recalc         = &omap2_clksel_recalc,
1189         .round_rate     = &omap2_clksel_round_rate,
1190         .set_rate       = &omap2_clksel_set_rate
1191 };
1192
1193 /*
1194  * SSI is in L3 management domain, its direct parent is core not l3,
1195  * many core power domain entities are grouped into the L3 clock
1196  * domain.
1197  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1198  *
1199  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1200  */
1201 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1202         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1203         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1204         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1205         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1206         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1207         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1208         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1209         { .div = 0 }
1210 };
1211
1212 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1213         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1214         { .parent = NULL }
1215 };
1216
1217 static struct clk ssi_ssr_sst_fck = {
1218         .name           = "ssi_fck",
1219         .parent         = &core_ck,
1220         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1221                                 DELAYED_APP,
1222         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
1223         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1224         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1225         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1226         .clksel         = ssi_ssr_sst_fck_clksel,
1227         .recalc         = &omap2_clksel_recalc,
1228         .round_rate     = &omap2_clksel_round_rate,
1229         .set_rate       = &omap2_clksel_set_rate
1230 };
1231
1232 /*
1233  * GFX clock domain
1234  *      Clocks:
1235  * GFX_FCLK, GFX_ICLK
1236  * GFX_CG1(2d), GFX_CG2(3d)
1237  *
1238  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1239  * The 2d and 3d clocks run at a hardware determined
1240  * divided value of fclk.
1241  *
1242  */
1243 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1244
1245 /*
1246  * These clksel_rate/clksel structs are shared between gfx_3d_fck and
1247  * gfx_2d_fck
1248  */
1249 static const struct clksel_rate gfx_fck_core_l3_rates[] = {
1250         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1251         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1252         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1253         { .div = 4, .val = 4, .flags = RATE_IN_243X },
1254         { .div = 0 }
1255 };
1256
1257 static const struct clksel gfx_fck_clksel[] = {
1258         { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates },
1259         { .parent = NULL },
1260 };
1261
1262 static struct clk gfx_3d_fck = {
1263         .name           = "gfx_3d_fck",
1264         .parent         = &core_l3_ck,
1265         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1266         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1267         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1268         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1269         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1270         .clksel         = gfx_fck_clksel,
1271         .recalc         = &omap2_clksel_recalc,
1272         .round_rate     = &omap2_clksel_round_rate,
1273         .set_rate       = &omap2_clksel_set_rate
1274 };
1275
1276 static struct clk gfx_2d_fck = {
1277         .name           = "gfx_2d_fck",
1278         .parent         = &core_l3_ck,
1279         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1280         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1281         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1282         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1283         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1284         .clksel         = gfx_fck_clksel,
1285         .recalc         = &omap2_clksel_recalc,
1286         .round_rate     = &omap2_clksel_round_rate,
1287         .set_rate       = &omap2_clksel_set_rate
1288 };
1289
1290 static struct clk gfx_ick = {
1291         .name           = "gfx_ick",            /* From l3 */
1292         .parent         = &core_l3_ck,
1293         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1294         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
1295         .enable_bit     = OMAP_EN_GFX_SHIFT,
1296         .recalc         = &followparent_recalc,
1297 };
1298
1299 /*
1300  * Modem clock domain (2430)
1301  *      CLOCKS:
1302  *              MDM_OSC_CLK
1303  *              MDM_ICLK
1304  * These clocks are usable in chassis mode only.
1305  */
1306 static const struct clksel_rate mdm_ick_core_rates[] = {
1307         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1308         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1309         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1310         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1311         { .div = 0 }
1312 };
1313
1314 static const struct clksel mdm_ick_clksel[] = {
1315         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1316         { .parent = NULL }
1317 };
1318
1319 static struct clk mdm_ick = {           /* used both as a ick and fck */
1320         .name           = "mdm_ick",
1321         .parent         = &core_ck,
1322         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1323         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1324         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1325         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1326         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1327         .clksel         = mdm_ick_clksel,
1328         .recalc         = &omap2_clksel_recalc,
1329         .round_rate     = &omap2_clksel_round_rate,
1330         .set_rate       = &omap2_clksel_set_rate
1331 };
1332
1333 static struct clk mdm_osc_ck = {
1334         .name           = "mdm_osc_ck",
1335         .parent         = &osc_ck,
1336         .flags          = CLOCK_IN_OMAP243X,
1337         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
1338         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1339         .recalc         = &followparent_recalc,
1340 };
1341
1342 /*
1343  * L4 clock management domain
1344  *
1345  * This domain contains lots of interface clocks from the L4 interface, some
1346  * functional clocks.   Fixed APLL functional source clocks are managed in
1347  * this domain.
1348  */
1349 static const struct clksel_rate l4_core_l3_rates[] = {
1350         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1351         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1352         { .div = 0 }
1353 };
1354
1355 static const struct clksel l4_clksel[] = {
1356         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1357         { .parent = NULL }
1358 };
1359
1360 static struct clk l4_ck = {             /* used both as an ick and fck */
1361         .name           = "l4_ck",
1362         .parent         = &core_l3_ck,
1363         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1364                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1365         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1366         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1367         .clksel         = l4_clksel,
1368         .recalc         = &omap2_clksel_recalc,
1369         .round_rate     = &omap2_clksel_round_rate,
1370         .set_rate       = &omap2_clksel_set_rate
1371 };
1372
1373 static struct clk ssi_l4_ick = {
1374         .name           = "ssi_l4_ick",
1375         .parent         = &l4_ck,
1376         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1377         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1378         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1379         .recalc         = &followparent_recalc,
1380 };
1381
1382 /*
1383  * DSS clock domain
1384  * CLOCKs:
1385  * DSS_L4_ICLK, DSS_L3_ICLK,
1386  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1387  *
1388  * DSS is both initiator and target.
1389  */
1390 /* XXX Add RATE_NOT_VALIDATED */
1391
1392 static const struct clksel_rate dss1_fck_sys_rates[] = {
1393         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1394         { .div = 0 }
1395 };
1396
1397 static const struct clksel_rate dss1_fck_core_rates[] = {
1398         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1399         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1400         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1401         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1402         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1403         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1404         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1405         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1406         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1407         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1408         { .div = 0 }
1409 };
1410
1411 static const struct clksel dss1_fck_clksel[] = {
1412         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1413         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1414         { .parent = NULL },
1415 };
1416
1417 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1418         .name           = "dss_ick",
1419         .parent         = &l4_ck,       /* really both l3 and l4 */
1420         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1421         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1422         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1423         .recalc         = &followparent_recalc,
1424 };
1425
1426 static struct clk dss1_fck = {
1427         .name           = "dss1_fck",
1428         .parent         = &core_ck,             /* Core or sys */
1429         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1430                                 DELAYED_APP,
1431         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1432         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1433         .init           = &omap2_init_clksel_parent,
1434         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1435         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1436         .clksel         = dss1_fck_clksel,
1437         .recalc         = &omap2_clksel_recalc,
1438         .round_rate     = &omap2_clksel_round_rate,
1439         .set_rate       = &omap2_clksel_set_rate
1440 };
1441
1442 static const struct clksel_rate dss2_fck_sys_rates[] = {
1443         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1444         { .div = 0 }
1445 };
1446
1447 static const struct clksel_rate dss2_fck_48m_rates[] = {
1448         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1449         { .div = 0 }
1450 };
1451
1452 static const struct clksel dss2_fck_clksel[] = {
1453         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1454         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1455         { .parent = NULL }
1456 };
1457
1458 static struct clk dss2_fck = {          /* Alt clk used in power management */
1459         .name           = "dss2_fck",
1460         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1461         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1462                                 DELAYED_APP,
1463         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1464         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1465         .init           = &omap2_init_clksel_parent,
1466         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1467         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1468         .clksel         = dss2_fck_clksel,
1469         .recalc         = &followparent_recalc,
1470 };
1471
1472 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1473         .name           = "dss_54m_fck",        /* 54m tv clk */
1474         .parent         = &func_54m_ck,
1475         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1476         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1477         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1478         .recalc         = &followparent_recalc,
1479 };
1480
1481 /*
1482  * CORE power domain ICLK & FCLK defines.
1483  * Many of the these can have more than one possible parent. Entries
1484  * here will likely have an L4 interface parent, and may have multiple
1485  * functional clock parents.
1486  */
1487 static const struct clksel_rate gpt_32k_rates[] = {
1488         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1489         { .div = 0 }
1490 };
1491
1492 static const struct clksel_rate gpt_sys_rates[] = {
1493         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1494         { .div = 0 }
1495 };
1496
1497 static const struct clksel_rate gpt_alt_rates[] = {
1498         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1499         { .div = 0 }
1500 };
1501
1502 static const struct clksel gpt_clksel[] = {
1503         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1504         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1505         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1506         { .parent = NULL },
1507 };
1508
1509 static struct clk gpt1_ick = {
1510         .name           = "gpt1_ick",
1511         .parent         = &l4_ck,
1512         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1513         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1514         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1515         .recalc         = &followparent_recalc,
1516 };
1517
1518 static struct clk gpt1_fck = {
1519         .name           = "gpt1_fck",
1520         .parent         = &func_32k_ck,
1521         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1522         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1523         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1524         .init           = &omap2_init_clksel_parent,
1525         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1526         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1527         .clksel         = gpt_clksel,
1528         .recalc         = &omap2_clksel_recalc,
1529         .round_rate     = &omap2_clksel_round_rate,
1530         .set_rate       = &omap2_clksel_set_rate
1531 };
1532
1533 static struct clk gpt2_ick = {
1534         .name           = "gpt2_ick",
1535         .parent         = &l4_ck,
1536         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1537         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1538         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1539         .recalc         = &followparent_recalc,
1540 };
1541
1542 static struct clk gpt2_fck = {
1543         .name           = "gpt2_fck",
1544         .parent         = &func_32k_ck,
1545         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1546         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1547         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1548         .init           = &omap2_init_clksel_parent,
1549         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1550         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1551         .clksel         = gpt_clksel,
1552         .recalc         = &omap2_clksel_recalc,
1553 };
1554
1555 static struct clk gpt3_ick = {
1556         .name           = "gpt3_ick",
1557         .parent         = &l4_ck,
1558         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1559         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1560         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1561         .recalc         = &followparent_recalc,
1562 };
1563
1564 static struct clk gpt3_fck = {
1565         .name           = "gpt3_fck",
1566         .parent         = &func_32k_ck,
1567         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1568         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1569         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1570         .init           = &omap2_init_clksel_parent,
1571         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1572         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1573         .clksel         = gpt_clksel,
1574         .recalc         = &omap2_clksel_recalc,
1575 };
1576
1577 static struct clk gpt4_ick = {
1578         .name           = "gpt4_ick",
1579         .parent         = &l4_ck,
1580         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1581         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1582         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1583         .recalc         = &followparent_recalc,
1584 };
1585
1586 static struct clk gpt4_fck = {
1587         .name           = "gpt4_fck",
1588         .parent         = &func_32k_ck,
1589         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1590         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1591         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1592         .init           = &omap2_init_clksel_parent,
1593         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1594         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1595         .clksel         = gpt_clksel,
1596         .recalc         = &omap2_clksel_recalc,
1597 };
1598
1599 static struct clk gpt5_ick = {
1600         .name           = "gpt5_ick",
1601         .parent         = &l4_ck,
1602         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1603         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1604         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1605         .recalc         = &followparent_recalc,
1606 };
1607
1608 static struct clk gpt5_fck = {
1609         .name           = "gpt5_fck",
1610         .parent         = &func_32k_ck,
1611         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1612         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1613         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1614         .init           = &omap2_init_clksel_parent,
1615         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1616         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1617         .clksel         = gpt_clksel,
1618         .recalc         = &omap2_clksel_recalc,
1619 };
1620
1621 static struct clk gpt6_ick = {
1622         .name           = "gpt6_ick",
1623         .parent         = &l4_ck,
1624         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1625         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1626         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1627         .recalc         = &followparent_recalc,
1628 };
1629
1630 static struct clk gpt6_fck = {
1631         .name           = "gpt6_fck",
1632         .parent         = &func_32k_ck,
1633         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1634         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1635         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1636         .init           = &omap2_init_clksel_parent,
1637         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1638         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1639         .clksel         = gpt_clksel,
1640         .recalc         = &omap2_clksel_recalc,
1641 };
1642
1643 static struct clk gpt7_ick = {
1644         .name           = "gpt7_ick",
1645         .parent         = &l4_ck,
1646         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1647         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1648         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1649         .recalc         = &followparent_recalc,
1650 };
1651
1652 static struct clk gpt7_fck = {
1653         .name           = "gpt7_fck",
1654         .parent         = &func_32k_ck,
1655         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1656         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1657         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1658         .init           = &omap2_init_clksel_parent,
1659         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1660         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1661         .clksel         = gpt_clksel,
1662         .recalc         = &omap2_clksel_recalc,
1663 };
1664
1665 static struct clk gpt8_ick = {
1666         .name           = "gpt8_ick",
1667         .parent         = &l4_ck,
1668         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1669         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1670         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1671         .recalc         = &followparent_recalc,
1672 };
1673
1674 static struct clk gpt8_fck = {
1675         .name           = "gpt8_fck",
1676         .parent         = &func_32k_ck,
1677         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1678         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1679         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1680         .init           = &omap2_init_clksel_parent,
1681         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1682         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1683         .clksel         = gpt_clksel,
1684         .recalc         = &omap2_clksel_recalc,
1685 };
1686
1687 static struct clk gpt9_ick = {
1688         .name           = "gpt9_ick",
1689         .parent         = &l4_ck,
1690         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1691         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1692         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1693         .recalc         = &followparent_recalc,
1694 };
1695
1696 static struct clk gpt9_fck = {
1697         .name           = "gpt9_fck",
1698         .parent         = &func_32k_ck,
1699         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1700         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1701         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1702         .init           = &omap2_init_clksel_parent,
1703         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1704         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1705         .clksel         = gpt_clksel,
1706         .recalc         = &omap2_clksel_recalc,
1707 };
1708
1709 static struct clk gpt10_ick = {
1710         .name           = "gpt10_ick",
1711         .parent         = &l4_ck,
1712         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1713         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1714         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1715         .recalc         = &followparent_recalc,
1716 };
1717
1718 static struct clk gpt10_fck = {
1719         .name           = "gpt10_fck",
1720         .parent         = &func_32k_ck,
1721         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1722         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1723         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1724         .init           = &omap2_init_clksel_parent,
1725         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1726         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1727         .clksel         = gpt_clksel,
1728         .recalc         = &omap2_clksel_recalc,
1729 };
1730
1731 static struct clk gpt11_ick = {
1732         .name           = "gpt11_ick",
1733         .parent         = &l4_ck,
1734         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1735         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1736         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1737         .recalc         = &followparent_recalc,
1738 };
1739
1740 static struct clk gpt11_fck = {
1741         .name           = "gpt11_fck",
1742         .parent         = &func_32k_ck,
1743         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1744         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1745         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1746         .init           = &omap2_init_clksel_parent,
1747         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1748         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1749         .clksel         = gpt_clksel,
1750         .recalc         = &omap2_clksel_recalc,
1751 };
1752
1753 static struct clk gpt12_ick = {
1754         .name           = "gpt12_ick",
1755         .parent         = &l4_ck,
1756         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1757         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1758         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1759         .recalc         = &followparent_recalc,
1760 };
1761
1762 static struct clk gpt12_fck = {
1763         .name           = "gpt12_fck",
1764         .parent         = &func_32k_ck,
1765         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1766         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1767         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1768         .init           = &omap2_init_clksel_parent,
1769         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1770         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1771         .clksel         = gpt_clksel,
1772         .recalc         = &omap2_clksel_recalc,
1773 };
1774
1775 static struct clk mcbsp1_ick = {
1776         .name           = "mcbsp1_ick",
1777         .parent         = &l4_ck,
1778         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1779         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1780         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1781         .recalc         = &followparent_recalc,
1782 };
1783
1784 static struct clk mcbsp1_fck = {
1785         .name           = "mcbsp1_fck",
1786         .parent         = &func_96m_ck,
1787         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1789         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1790         .recalc         = &followparent_recalc,
1791 };
1792
1793 static struct clk mcbsp2_ick = {
1794         .name           = "mcbsp2_ick",
1795         .parent         = &l4_ck,
1796         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1797         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1798         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1799         .recalc         = &followparent_recalc,
1800 };
1801
1802 static struct clk mcbsp2_fck = {
1803         .name           = "mcbsp2_fck",
1804         .parent         = &func_96m_ck,
1805         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1806         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1807         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1808         .recalc         = &followparent_recalc,
1809 };
1810
1811 static struct clk mcbsp3_ick = {
1812         .name           = "mcbsp3_ick",
1813         .parent         = &l4_ck,
1814         .flags          = CLOCK_IN_OMAP243X,
1815         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1816         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1817         .recalc         = &followparent_recalc,
1818 };
1819
1820 static struct clk mcbsp3_fck = {
1821         .name           = "mcbsp3_fck",
1822         .parent         = &func_96m_ck,
1823         .flags          = CLOCK_IN_OMAP243X,
1824         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1825         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1826         .recalc         = &followparent_recalc,
1827 };
1828
1829 static struct clk mcbsp4_ick = {
1830         .name           = "mcbsp4_ick",
1831         .parent         = &l4_ck,
1832         .flags          = CLOCK_IN_OMAP243X,
1833         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1834         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 static struct clk mcbsp4_fck = {
1839         .name           = "mcbsp4_fck",
1840         .parent         = &func_96m_ck,
1841         .flags          = CLOCK_IN_OMAP243X,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1843         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1844         .recalc         = &followparent_recalc,
1845 };
1846
1847 static struct clk mcbsp5_ick = {
1848         .name           = "mcbsp5_ick",
1849         .parent         = &l4_ck,
1850         .flags          = CLOCK_IN_OMAP243X,
1851         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1852         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1853         .recalc         = &followparent_recalc,
1854 };
1855
1856 static struct clk mcbsp5_fck = {
1857         .name           = "mcbsp5_fck",
1858         .parent         = &func_96m_ck,
1859         .flags          = CLOCK_IN_OMAP243X,
1860         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1861         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1862         .recalc         = &followparent_recalc,
1863 };
1864
1865 static struct clk mcspi1_ick = {
1866         .name           = "mcspi_ick",
1867         .id             = 1,
1868         .parent         = &l4_ck,
1869         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1870         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1871         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1872         .recalc         = &followparent_recalc,
1873 };
1874
1875 static struct clk mcspi1_fck = {
1876         .name           = "mcspi_fck",
1877         .id             = 1,
1878         .parent         = &func_48m_ck,
1879         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1880         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1881         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 static struct clk mcspi2_ick = {
1886         .name           = "mcspi_ick",
1887         .id             = 2,
1888         .parent         = &l4_ck,
1889         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1890         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1891         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1892         .recalc         = &followparent_recalc,
1893 };
1894
1895 static struct clk mcspi2_fck = {
1896         .name           = "mcspi_fck",
1897         .id             = 2,
1898         .parent         = &func_48m_ck,
1899         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1900         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1901         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1902         .recalc         = &followparent_recalc,
1903 };
1904
1905 static struct clk mcspi3_ick = {
1906         .name           = "mcspi_ick",
1907         .id             = 3,
1908         .parent         = &l4_ck,
1909         .flags          = CLOCK_IN_OMAP243X,
1910         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1911         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1912         .recalc         = &followparent_recalc,
1913 };
1914
1915 static struct clk mcspi3_fck = {
1916         .name           = "mcspi_fck",
1917         .id             = 3,
1918         .parent         = &func_48m_ck,
1919         .flags          = CLOCK_IN_OMAP243X,
1920         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1921         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1922         .recalc         = &followparent_recalc,
1923 };
1924
1925 static struct clk uart1_ick = {
1926         .name           = "uart1_ick",
1927         .parent         = &l4_ck,
1928         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1929         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1930         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1931         .recalc         = &followparent_recalc,
1932 };
1933
1934 static struct clk uart1_fck = {
1935         .name           = "uart1_fck",
1936         .parent         = &func_48m_ck,
1937         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1938         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1939         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk uart2_ick = {
1944         .name           = "uart2_ick",
1945         .parent         = &l4_ck,
1946         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1947         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1948         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1949         .recalc         = &followparent_recalc,
1950 };
1951
1952 static struct clk uart2_fck = {
1953         .name           = "uart2_fck",
1954         .parent         = &func_48m_ck,
1955         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1957         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1958         .recalc         = &followparent_recalc,
1959 };
1960
1961 static struct clk uart3_ick = {
1962         .name           = "uart3_ick",
1963         .parent         = &l4_ck,
1964         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1965         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1966         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk uart3_fck = {
1971         .name           = "uart3_fck",
1972         .parent         = &func_48m_ck,
1973         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1974         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1975         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk gpios_ick = {
1980         .name           = "gpios_ick",
1981         .parent         = &l4_ck,
1982         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1983         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1984         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk gpios_fck = {
1989         .name           = "gpios_fck",
1990         .parent         = &func_32k_ck,
1991         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1992         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1993         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk mpu_wdt_ick = {
1998         .name           = "mpu_wdt_ick",
1999         .parent         = &l4_ck,
2000         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2001         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2002         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 static struct clk mpu_wdt_fck = {
2007         .name           = "mpu_wdt_fck",
2008         .parent         = &func_32k_ck,
2009         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2010         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2011         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2012         .recalc         = &followparent_recalc,
2013 };
2014
2015 static struct clk sync_32k_ick = {
2016         .name           = "sync_32k_ick",
2017         .parent         = &l4_ck,
2018         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2019         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2020         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2021         .recalc         = &followparent_recalc,
2022 };
2023 static struct clk wdt1_ick = {
2024         .name           = "wdt1_ick",
2025         .parent         = &l4_ck,
2026         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2027         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2028         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2029         .recalc         = &followparent_recalc,
2030 };
2031 static struct clk omapctrl_ick = {
2032         .name           = "omapctrl_ick",
2033         .parent         = &l4_ck,
2034         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2035         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2036         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2037         .recalc         = &followparent_recalc,
2038 };
2039 static struct clk icr_ick = {
2040         .name           = "icr_ick",
2041         .parent         = &l4_ck,
2042         .flags          = CLOCK_IN_OMAP243X,
2043         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2044         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 static struct clk cam_ick = {
2049         .name           = "cam_ick",
2050         .parent         = &l4_ck,
2051         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2052         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2053         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2054         .recalc         = &followparent_recalc,
2055 };
2056
2057 static struct clk cam_fck = {
2058         .name           = "cam_fck",
2059         .parent         = &func_96m_ck,
2060         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2061         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2062         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk mailboxes_ick = {
2067         .name           = "mailboxes_ick",
2068         .parent         = &l4_ck,
2069         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2070         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2071         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 static struct clk wdt4_ick = {
2076         .name           = "wdt4_ick",
2077         .parent         = &l4_ck,
2078         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2079         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2080         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2081         .recalc         = &followparent_recalc,
2082 };
2083
2084 static struct clk wdt4_fck = {
2085         .name           = "wdt4_fck",
2086         .parent         = &func_32k_ck,
2087         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2088         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2089         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2090         .recalc         = &followparent_recalc,
2091 };
2092
2093 static struct clk wdt3_ick = {
2094         .name           = "wdt3_ick",
2095         .parent         = &l4_ck,
2096         .flags          = CLOCK_IN_OMAP242X,
2097         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2098         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2099         .recalc         = &followparent_recalc,
2100 };
2101
2102 static struct clk wdt3_fck = {
2103         .name           = "wdt3_fck",
2104         .parent         = &func_32k_ck,
2105         .flags          = CLOCK_IN_OMAP242X,
2106         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2107         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2108         .recalc         = &followparent_recalc,
2109 };
2110
2111 static struct clk mspro_ick = {
2112         .name           = "mspro_ick",
2113         .parent         = &l4_ck,
2114         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2115         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2116         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk mspro_fck = {
2121         .name           = "mspro_fck",
2122         .parent         = &func_96m_ck,
2123         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2124         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2125         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2126         .recalc         = &followparent_recalc,
2127 };
2128
2129 static struct clk mmc_ick = {
2130         .name           = "mmc_ick",
2131         .parent         = &l4_ck,
2132         .flags          = CLOCK_IN_OMAP242X,
2133         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2134         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2135         .recalc         = &followparent_recalc,
2136 };
2137
2138 static struct clk mmc_fck = {
2139         .name           = "mmc_fck",
2140         .parent         = &func_96m_ck,
2141         .flags          = CLOCK_IN_OMAP242X,
2142         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2143         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2144         .recalc         = &followparent_recalc,
2145 };
2146
2147 static struct clk fac_ick = {
2148         .name           = "fac_ick",
2149         .parent         = &l4_ck,
2150         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2151         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2152         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2153         .recalc         = &followparent_recalc,
2154 };
2155
2156 static struct clk fac_fck = {
2157         .name           = "fac_fck",
2158         .parent         = &func_12m_ck,
2159         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2160         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2161         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2162         .recalc         = &followparent_recalc,
2163 };
2164
2165 static struct clk eac_ick = {
2166         .name           = "eac_ick",
2167         .parent         = &l4_ck,
2168         .flags          = CLOCK_IN_OMAP242X,
2169         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2170         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 static struct clk eac_fck = {
2175         .name           = "eac_fck",
2176         .parent         = &func_96m_ck,
2177         .flags          = CLOCK_IN_OMAP242X,
2178         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2179         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk hdq_ick = {
2184         .name           = "hdq_ick",
2185         .parent         = &l4_ck,
2186         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2187         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2188         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2189         .recalc         = &followparent_recalc,
2190 };
2191
2192 static struct clk hdq_fck = {
2193         .name           = "hdq_fck",
2194         .parent         = &func_12m_ck,
2195         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2196         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2197         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2198         .recalc         = &followparent_recalc,
2199 };
2200
2201 static struct clk i2c2_ick = {
2202         .name           = "i2c_ick",
2203         .id             = 2,
2204         .parent         = &l4_ck,
2205         .flags          = CLOCK_IN_OMAP242X,
2206         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2207         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 static struct clk i2c2_fck = {
2212         .name           = "i2c_fck",
2213         .id             = 2,
2214         .parent         = &func_12m_ck,
2215         .flags          = CLOCK_IN_OMAP242X,
2216         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2217         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2218         .recalc         = &followparent_recalc,
2219 };
2220
2221 static struct clk i2chs2_fck = {
2222         .name           = "i2chs_fck",
2223         .id             = 2,
2224         .parent         = &func_96m_ck,
2225         .flags          = CLOCK_IN_OMAP243X,
2226         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2227         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2228         .recalc         = &followparent_recalc,
2229 };
2230
2231 static struct clk i2c1_ick = {
2232         .name           = "i2c_ick",
2233         .id             = 1,
2234         .parent         = &l4_ck,
2235         .flags          = CLOCK_IN_OMAP242X,
2236         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2237         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2238         .recalc         = &followparent_recalc,
2239 };
2240
2241 static struct clk i2c1_fck = {
2242         .name           = "i2c_fck",
2243         .id             = 1,
2244         .parent         = &func_12m_ck,
2245         .flags          = CLOCK_IN_OMAP242X,
2246         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2247         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2248         .recalc         = &followparent_recalc,
2249 };
2250
2251 static struct clk i2chs1_fck = {
2252         .name           = "i2chs_fck",
2253         .id             = 1,
2254         .parent         = &func_96m_ck,
2255         .flags          = CLOCK_IN_OMAP243X,
2256         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2257         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2258         .recalc         = &followparent_recalc,
2259 };
2260
2261 static struct clk vlynq_ick = {
2262         .name           = "vlynq_ick",
2263         .parent         = &core_l3_ck,
2264         .flags          = CLOCK_IN_OMAP242X,
2265         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2266         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2267         .recalc         = &followparent_recalc,
2268 };
2269
2270 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2271         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2272         { .div = 0 }
2273 };
2274
2275 static const struct clksel_rate vlynq_fck_core_rates[] = {
2276         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2277         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2278         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2279         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2280         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2281         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2282         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2283         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2284         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2285         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2286         { .div = 0 }
2287 };
2288
2289 static const struct clksel vlynq_fck_clksel[] = {
2290         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2291         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2292         { .parent = NULL }
2293 };
2294
2295 static struct clk vlynq_fck = {
2296         .name           = "vlynq_fck",
2297         .parent         = &func_96m_ck,
2298         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2299         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2300         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2301         .init           = &omap2_init_clksel_parent,
2302         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2303         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2304         .clksel         = vlynq_fck_clksel,
2305         .recalc         = &omap2_clksel_recalc,
2306         .round_rate     = &omap2_clksel_round_rate,
2307         .set_rate       = &omap2_clksel_set_rate
2308 };
2309
2310 static struct clk sdrc_ick = {
2311         .name           = "sdrc_ick",
2312         .parent         = &l4_ck,
2313         .flags          = CLOCK_IN_OMAP243X,
2314         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2315         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2316         .recalc         = &followparent_recalc,
2317 };
2318
2319 static struct clk des_ick = {
2320         .name           = "des_ick",
2321         .parent         = &l4_ck,
2322         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2323         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2324         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2325         .recalc         = &followparent_recalc,
2326 };
2327
2328 static struct clk sha_ick = {
2329         .name           = "sha_ick",
2330         .parent         = &l4_ck,
2331         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2332         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2333         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2334         .recalc         = &followparent_recalc,
2335 };
2336
2337 static struct clk rng_ick = {
2338         .name           = "rng_ick",
2339         .parent         = &l4_ck,
2340         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2342         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2343         .recalc         = &followparent_recalc,
2344 };
2345
2346 static struct clk aes_ick = {
2347         .name           = "aes_ick",
2348         .parent         = &l4_ck,
2349         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2350         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2351         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 static struct clk pka_ick = {
2356         .name           = "pka_ick",
2357         .parent         = &l4_ck,
2358         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2359         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2360         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2361         .recalc         = &followparent_recalc,
2362 };
2363
2364 static struct clk usb_fck = {
2365         .name           = "usb_fck",
2366         .parent         = &func_48m_ck,
2367         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2369         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2370         .recalc         = &followparent_recalc,
2371 };
2372
2373 static struct clk usbhs_ick = {
2374         .name           = "usbhs_ick",
2375         .parent         = &core_l3_ck,
2376         .flags          = CLOCK_IN_OMAP243X,
2377         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2378         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2379         .recalc         = &followparent_recalc,
2380 };
2381
2382 static struct clk mmchs1_ick = {
2383         .name           = "mmchs1_ick",
2384         .parent         = &l4_ck,
2385         .flags          = CLOCK_IN_OMAP243X,
2386         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2387         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2388         .recalc         = &followparent_recalc,
2389 };
2390
2391 static struct clk mmchs1_fck = {
2392         .name           = "mmchs1_fck",
2393         .parent         = &func_96m_ck,
2394         .flags          = CLOCK_IN_OMAP243X,
2395         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2396         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2397         .recalc         = &followparent_recalc,
2398 };
2399
2400 static struct clk mmchs2_ick = {
2401         .name           = "mmchs2_ick",
2402         .parent         = &l4_ck,
2403         .flags          = CLOCK_IN_OMAP243X,
2404         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2405         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2406         .recalc         = &followparent_recalc,
2407 };
2408
2409 static struct clk mmchs2_fck = {
2410         .name           = "mmchs2_fck",
2411         .parent         = &func_96m_ck,
2412         .flags          = CLOCK_IN_OMAP243X,
2413         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2414         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk gpio5_ick = {
2419         .name           = "gpio5_ick",
2420         .parent         = &l4_ck,
2421         .flags          = CLOCK_IN_OMAP243X,
2422         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2423         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2424         .recalc         = &followparent_recalc,
2425 };
2426
2427 static struct clk gpio5_fck = {
2428         .name           = "gpio5_fck",
2429         .parent         = &func_32k_ck,
2430         .flags          = CLOCK_IN_OMAP243X,
2431         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2432         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2433         .recalc         = &followparent_recalc,
2434 };
2435
2436 static struct clk mdm_intc_ick = {
2437         .name           = "mdm_intc_ick",
2438         .parent         = &l4_ck,
2439         .flags          = CLOCK_IN_OMAP243X,
2440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2441         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2442         .recalc         = &followparent_recalc,
2443 };
2444
2445 static struct clk mmchsdb1_fck = {
2446         .name           = "mmchsdb1_fck",
2447         .parent         = &func_32k_ck,
2448         .flags          = CLOCK_IN_OMAP243X,
2449         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2450         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2451         .recalc         = &followparent_recalc,
2452 };
2453
2454 static struct clk mmchsdb2_fck = {
2455         .name           = "mmchsdb2_fck",
2456         .parent         = &func_32k_ck,
2457         .flags          = CLOCK_IN_OMAP243X,
2458         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2459         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2460         .recalc         = &followparent_recalc,
2461 };
2462
2463 /*
2464  * This clock is a composite clock which does entire set changes then
2465  * forces a rebalance. It keys on the MPU speed, but it really could
2466  * be any key speed part of a set in the rate table.
2467  *
2468  * to really change a set, you need memory table sets which get changed
2469  * in sram, pre-notifiers & post notifiers, changing the top set, without
2470  * having low level display recalc's won't work... this is why dpm notifiers
2471  * work, isr's off, walk a list of clocks already _off_ and not messing with
2472  * the bus.
2473  *
2474  * This clock should have no parent. It embodies the entire upper level
2475  * active set. A parent will mess up some of the init also.
2476  */
2477 static struct clk virt_prcm_set = {
2478         .name           = "virt_prcm_set",
2479         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2480                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2481         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2482         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2483         .set_rate       = &omap2_select_table_rate,
2484         .round_rate     = &omap2_round_to_table_rate,
2485 };
2486
2487 static struct clk *onchip_clks[] __initdata = {
2488         /* external root sources */
2489         &func_32k_ck,
2490         &osc_ck,
2491         &sys_ck,
2492         &alt_ck,
2493         /* internal analog sources */
2494         &dpll_ck,
2495         &apll96_ck,
2496         &apll54_ck,
2497         /* internal prcm root sources */
2498         &func_54m_ck,
2499         &core_ck,
2500         &func_96m_ck,
2501         &func_48m_ck,
2502         &func_12m_ck,
2503         &wdt1_osc_ck,
2504         &sys_clkout_src,
2505         &sys_clkout,
2506         &sys_clkout2_src,
2507         &sys_clkout2,
2508         &emul_ck,
2509         /* mpu domain clocks */
2510         &mpu_ck,
2511         /* dsp domain clocks */
2512         &iva2_1_fck,            /* 2430 */
2513         &iva2_1_ick,
2514         &dsp_ick,               /* 2420 */
2515         &dsp_fck,
2516         &iva1_ifck,
2517         &iva1_mpu_int_ifck,
2518         /* GFX domain clocks */
2519         &gfx_3d_fck,
2520         &gfx_2d_fck,
2521         &gfx_ick,
2522         /* Modem domain clocks */
2523         &mdm_ick,
2524         &mdm_osc_ck,
2525         /* DSS domain clocks */
2526         &dss_ick,
2527         &dss1_fck,
2528         &dss2_fck,
2529         &dss_54m_fck,
2530         /* L3 domain clocks */
2531         &core_l3_ck,
2532         &ssi_ssr_sst_fck,
2533         &usb_l4_ick,
2534         /* L4 domain clocks */
2535         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2536         &ssi_l4_ick,
2537         /* virtual meta-group clock */
2538         &virt_prcm_set,
2539         /* general l4 interface ck, multi-parent functional clk */
2540         &gpt1_ick,
2541         &gpt1_fck,
2542         &gpt2_ick,
2543         &gpt2_fck,
2544         &gpt3_ick,
2545         &gpt3_fck,
2546         &gpt4_ick,
2547         &gpt4_fck,
2548         &gpt5_ick,
2549         &gpt5_fck,
2550         &gpt6_ick,
2551         &gpt6_fck,
2552         &gpt7_ick,
2553         &gpt7_fck,
2554         &gpt8_ick,
2555         &gpt8_fck,
2556         &gpt9_ick,
2557         &gpt9_fck,
2558         &gpt10_ick,
2559         &gpt10_fck,
2560         &gpt11_ick,
2561         &gpt11_fck,
2562         &gpt12_ick,
2563         &gpt12_fck,
2564         &mcbsp1_ick,
2565         &mcbsp1_fck,
2566         &mcbsp2_ick,
2567         &mcbsp2_fck,
2568         &mcbsp3_ick,
2569         &mcbsp3_fck,
2570         &mcbsp4_ick,
2571         &mcbsp4_fck,
2572         &mcbsp5_ick,
2573         &mcbsp5_fck,
2574         &mcspi1_ick,
2575         &mcspi1_fck,
2576         &mcspi2_ick,
2577         &mcspi2_fck,
2578         &mcspi3_ick,
2579         &mcspi3_fck,
2580         &uart1_ick,
2581         &uart1_fck,
2582         &uart2_ick,
2583         &uart2_fck,
2584         &uart3_ick,
2585         &uart3_fck,
2586         &gpios_ick,
2587         &gpios_fck,
2588         &mpu_wdt_ick,
2589         &mpu_wdt_fck,
2590         &sync_32k_ick,
2591         &wdt1_ick,
2592         &omapctrl_ick,
2593         &icr_ick,
2594         &cam_fck,
2595         &cam_ick,
2596         &mailboxes_ick,
2597         &wdt4_ick,
2598         &wdt4_fck,
2599         &wdt3_ick,
2600         &wdt3_fck,
2601         &mspro_ick,
2602         &mspro_fck,
2603         &mmc_ick,
2604         &mmc_fck,
2605         &fac_ick,
2606         &fac_fck,
2607         &eac_ick,
2608         &eac_fck,
2609         &hdq_ick,
2610         &hdq_fck,
2611         &i2c1_ick,
2612         &i2c1_fck,
2613         &i2chs1_fck,
2614         &i2c2_ick,
2615         &i2c2_fck,
2616         &i2chs2_fck,
2617         &vlynq_ick,
2618         &vlynq_fck,
2619         &sdrc_ick,
2620         &des_ick,
2621         &sha_ick,
2622         &rng_ick,
2623         &aes_ick,
2624         &pka_ick,
2625         &usb_fck,
2626         &usbhs_ick,
2627         &mmchs1_ick,
2628         &mmchs1_fck,
2629         &mmchs2_ick,
2630         &mmchs2_fck,
2631         &gpio5_ick,
2632         &gpio5_fck,
2633         &mdm_intc_ick,
2634         &mmchsdb1_fck,
2635         &mmchsdb2_fck,
2636 };
2637
2638 #endif