arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap24xx/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  19
  20 static void omap2_sys_clk_recalc(struct clk * clk);
  21 static void omap2_clksel_recalc(struct clk * clk);
  22 static void omap2_followparent_recalc(struct clk * clk);
  23 static void omap2_propagate_rate(struct clk * clk);
  24 static void omap2_mpu_recalc(struct clk * clk);
  25 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  26 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  27 static void omap2_clk_disable(struct clk *clk);
  28 static void omap2_sys_clk_recalc(struct clk * clk);
  29 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
  30 static u32 omap2_clksel_get_divisor(struct clk *clk);
  31
  32
  33 #define RATE_IN_242X    (1 << 0)
  34 #define RATE_IN_243X    (1 << 1)
  35
  36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  37  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  38  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  39  */
  40 struct prcm_config {
  41         unsigned long xtal_speed;       /* crystal rate */
  42         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  43         unsigned long mpu_speed;        /* speed of MPU */
  44         unsigned long cm_clksel_mpu;    /* mpu divider */
  45         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  46         unsigned long cm_clksel_gfx;    /* gfx dividers */
  47         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  48         unsigned long cm_clksel1_pll;   /* m,n */
  49         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  50         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  51         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  52         unsigned char flags;
  53 };
  54
  55 /* Mask for clksel which support parent settign in set_rate */
  56 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
  57                         CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
  58
  59 /* Mask for clksel regs which support rate operations */
  60 #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
  61                         CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
  62                         CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
  63                         CM_SYSCLKOUT_SEL1)
  64
  65 /*
  66  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  67  * These configurations are characterized by voltage and speed for clocks.
  68  * The device is only validated for certain combinations. One way to express
  69  * these combinations is via the 'ratio's' which the clocks operate with
  70  * respect to each other. These ratio sets are for a given voltage/DPLL
  71  * setting. All configurations can be described by a DPLL setting and a ratio
  72  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  73  *
  74  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  75  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  76  * 2430 (iva2.1, NOdsp, mdm)
  77  */
  78
  79 /* Core fields for cm_clksel, not ratio governed */
  80 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  81 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  82 #define RX_CLKSEL_SSI                   (0x5 << 20)
  83
  84 /*-------------------------------------------------------------------------
  85  * Voltage/DPLL ratios
  86  *-------------------------------------------------------------------------*/
  87
  88 /* 2430 Ratio's, 2430-Ratio Config 1 */
  89 #define R1_CLKSEL_L3                    (4 << 0)
  90 #define R1_CLKSEL_L4                    (2 << 5)
  91 #define R1_CLKSEL_USB                   (4 << 25)
  92 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  93                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  94                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  95 #define R1_CLKSEL_MPU                   (2 << 0)
  96 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  97 #define R1_CLKSEL_DSP                   (2 << 0)
  98 #define R1_CLKSEL_DSP_IF                (2 << 5)
  99 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 100 #define R1_CLKSEL_GFX                   (2 << 0)
 101 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 102 #define R1_CLKSEL_MDM                   (4 << 0)
 103 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 104
 105 /* 2430-Ratio Config 2 */
 106 #define R2_CLKSEL_L3                    (6 << 0)
 107 #define R2_CLKSEL_L4                    (2 << 5)
 108 #define R2_CLKSEL_USB                   (2 << 25)
 109 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 110                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 111                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 112 #define R2_CLKSEL_MPU                   (2 << 0)
 113 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 114 #define R2_CLKSEL_DSP                   (2 << 0)
 115 #define R2_CLKSEL_DSP_IF                (3 << 5)
 116 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 117 #define R2_CLKSEL_GFX                   (2 << 0)
 118 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 119 #define R2_CLKSEL_MDM                   (6 << 0)
 120 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 121
 122 /* 2430-Ratio Bootm (BYPASS) */
 123 #define RB_CLKSEL_L3                    (1 << 0)
 124 #define RB_CLKSEL_L4                    (1 << 5)
 125 #define RB_CLKSEL_USB                   (1 << 25)
 126 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 127                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 128                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 129 #define RB_CLKSEL_MPU                   (1 << 0)
 130 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 131 #define RB_CLKSEL_DSP                   (1 << 0)
 132 #define RB_CLKSEL_DSP_IF                (1 << 5)
 133 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 134 #define RB_CLKSEL_GFX                   (1 << 0)
 135 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 136 #define RB_CLKSEL_MDM                   (1 << 0)
 137 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 138
 139 /* 2420 Ratio Equivalents */
 140 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 141 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 142
 143 /* 2420-PRCM III 532MHz core */
 144 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 145 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 146 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 147 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 148                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 149                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 150                                         RIII_CLKSEL_L3
 151 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 152 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 153 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 154 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 155 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 156 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 157 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 158 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 159                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 160                                         RIII_CLKSEL_DSP
 161 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 162 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 163
 164 /* 2420-PRCM II 600MHz core */
 165 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 166 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 167 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 168 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 169                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 170                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 171                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 172 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 173 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 174 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 175 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 176 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 177 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 178 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 179 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 180                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 181                                         RII_CLKSEL_DSP
 182 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 183 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 184
 185 /* 2420-PRCM I 660MHz core */
 186 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 187 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 188 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 189 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 190                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 191                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 192                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 193 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 194 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 195 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 196 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 197 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 198 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 199 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 200 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 201                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 202                                         RI_CLKSEL_DSP
 203 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 204 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 205
 206 /* 2420-PRCM VII (boot) */
 207 #define RVII_CLKSEL_L3                  (1 << 0)
 208 #define RVII_CLKSEL_L4                  (1 << 5)
 209 #define RVII_CLKSEL_DSS1                (1 << 8)
 210 #define RVII_CLKSEL_DSS2                (0 << 13)
 211 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 212 #define RVII_CLKSEL_SSI                 (1 << 20)
 213 #define RVII_CLKSEL_USB                 (1 << 25)
 214
 215 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 216                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 217                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 218
 219 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 220 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 221
 222 #define RVII_CLKSEL_DSP                 (1 << 0)
 223 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 224 #define RVII_SYNC_DSP                   (0 << 7)
 225 #define RVII_CLKSEL_IVA                 (1 << 8)
 226 #define RVII_SYNC_IVA                   (0 << 13)
 227 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 228                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 229
 230 #define RVII_CLKSEL_GFX                 (1 << 0)
 231 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 232
 233 /*-------------------------------------------------------------------------
 234  * 2430 Target modes: Along with each configuration the CPU has several
 235  * modes which goes along with them. Modes mainly are the addition of
 236  * describe DPLL combinations to go along with a ratio.
 237  *-------------------------------------------------------------------------*/
 238
 239 /* Hardware governed */
 240 #define MX_48M_SRC                      (0 << 3)
 241 #define MX_54M_SRC                      (0 << 5)
 242 #define MX_APLLS_CLIKIN_12              (3 << 23)
 243 #define MX_APLLS_CLIKIN_13              (2 << 23)
 244 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 245
 246 /*
 247  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 248  * #2   (ratio1) baseport-target
 249  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 250  */
 251 #define M5A_DPLL_MULT_12                (133 << 12)
 252 #define M5A_DPLL_DIV_12                 (5 << 8)
 253 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 254                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 255                                         MX_APLLS_CLIKIN_12
 256 #define M5A_DPLL_MULT_13                (266 << 12)
 257 #define M5A_DPLL_DIV_13                 (12 << 8)
 258 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 259                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 260                                         MX_APLLS_CLIKIN_13
 261 #define M5A_DPLL_MULT_19                (180 << 12)
 262 #define M5A_DPLL_DIV_19                 (12 << 8)
 263 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 264                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 265                                         MX_APLLS_CLIKIN_19_2
 266 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 267 #define M5B_DPLL_MULT_12                (50 << 12)
 268 #define M5B_DPLL_DIV_12                 (2 << 8)
 269 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 270                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 271                                         MX_APLLS_CLIKIN_12
 272 #define M5B_DPLL_MULT_13                (200 << 12)
 273 #define M5B_DPLL_DIV_13                 (12 << 8)
 274
 275 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 276                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 277                                         MX_APLLS_CLIKIN_13
 278 #define M5B_DPLL_MULT_19                (125 << 12)
 279 #define M5B_DPLL_DIV_19                 (31 << 8)
 280 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 281                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 282                                         MX_APLLS_CLIKIN_19_2
 283 /*
 284  * #4   (ratio2)
 285  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 286  */
 287 #define M3_DPLL_MULT_12                 (55 << 12)
 288 #define M3_DPLL_DIV_12                  (1 << 8)
 289 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 290                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 291                                         MX_APLLS_CLIKIN_12
 292 #define M3_DPLL_MULT_13                 (330 << 12)
 293 #define M3_DPLL_DIV_13                  (12 << 8)
 294 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 295                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 296                                         MX_APLLS_CLIKIN_13
 297 #define M3_DPLL_MULT_19                 (275 << 12)
 298 #define M3_DPLL_DIV_19                  (15 << 8)
 299 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 300                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 301                                         MX_APLLS_CLIKIN_19_2
 302 /* boot (boot) */
 303 #define MB_DPLL_MULT                    (1 << 12)
 304 #define MB_DPLL_DIV                     (0 << 8)
 305 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 306                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 307
 308 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 309                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 310
 311 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 312                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 313
 314 /*
 315  * 2430 - chassis (sedna)
 316  * 165 (ratio1) same as above #2
 317  * 150 (ratio1)
 318  * 133 (ratio2) same as above #4
 319  * 110 (ratio2) same as above #3
 320  * 104 (ratio2)
 321  * boot (boot)
 322  */
 323
 324 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 325 #define MI_DPLL_MULT_12                 (55 << 12)
 326 #define MI_DPLL_DIV_12                  (1 << 8)
 327 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 328                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 329                                         MX_APLLS_CLIKIN_12
 330
 331 /*
 332  * 2420 Equivalent - mode registers
 333  * PRCM II , target DPLL = 2*300MHz = 600MHz
 334  */
 335 #define MII_DPLL_MULT_12                (50 << 12)
 336 #define MII_DPLL_DIV_12                 (1 << 8)
 337 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 338                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 339                                         MX_APLLS_CLIKIN_12
 340 #define MII_DPLL_MULT_13                (300 << 12)
 341 #define MII_DPLL_DIV_13                 (12 << 8)
 342 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 343                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 344                                         MX_APLLS_CLIKIN_13
 345
 346 /* PRCM III target DPLL = 2*266 = 532MHz*/
 347 #define MIII_DPLL_MULT_12               (133 << 12)
 348 #define MIII_DPLL_DIV_12                (5 << 8)
 349 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 350                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 351                                         MX_APLLS_CLIKIN_12
 352 #define MIII_DPLL_MULT_13               (266 << 12)
 353 #define MIII_DPLL_DIV_13                (12 << 8)
 354 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 355                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 356                                         MX_APLLS_CLIKIN_13
 357
 358 /* PRCM VII (boot bypass) */
 359 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 360 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 361
 362 /* High and low operation value */
 363 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 364 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 365
 366 /*
 367  * These represent optimal values for common parts, it won't work for all.
 368  * As long as you scale down, most parameters are still work, they just
 369  * become sub-optimal. The RFR value goes in the oppisite direction. If you
 370  * don't adjust it down as your clock period increases the refresh interval
 371  * will not be met. Setting all parameters for complete worst case may work,
 372  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 373  * unlocked and their value needs run time calibration. A dynamic call is
 374  * need for that as no single right value exists acorss production samples.
 375  *
 376  * Only the FULL speed values are given. Current code is such that rate
 377  * changes must be made at DPLLoutx2. The actual value adjustment for low
 378  * frequency operation will be handled by omap_set_performance()
 379  *
 380  * By having the boot loader boot up in the fastest L4 speed available likely
 381  * will result in something which you can switch between.
 382  */
 383 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 384 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 385 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 386 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 387 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 388
 389 /* MPU speed defines */
 390 #define S12M    12000000
 391 #define S13M    13000000
 392 #define S19M    19200000
 393 #define S26M    26000000
 394 #define S100M   100000000
 395 #define S133M   133000000
 396 #define S150M   150000000
 397 #define S165M   165000000
 398 #define S200M   200000000
 399 #define S266M   266000000
 400 #define S300M   300000000
 401 #define S330M   330000000
 402 #define S400M   400000000
 403 #define S532M   532000000
 404 #define S600M   600000000
 405 #define S660M   660000000
 406
 407 /*-------------------------------------------------------------------------
 408  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 409  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 410  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 411  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 412  *
 413  * Filling in table based on H4 boards and 2430-SDPs variants available.
 414  * There are quite a few more rates combinations which could be defined.
 415  *
 416  * When multiple values are defiend the start up will try and choose the
 417  * fastest one. If a 'fast' value is defined, then automatically, the /2
 418  * one should be included as it can be used.    Generally having more that
 419  * one fast set does not make sense, as static timings need to be changed
 420  * to change the set.    The exception is the bypass setting which is
 421  * availble for low power bypass.
 422  *
 423  * Note: This table needs to be sorted, fastest to slowest.
 424  *-------------------------------------------------------------------------*/
 425 static struct prcm_config rate_table[] = {
 426         /* PRCM I - FAST */
 427         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 428                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 429                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 430                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 431                 RATE_IN_242X},
 432
 433         /* PRCM II - FAST */
 434         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 435                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 436                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 437                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 438                 RATE_IN_242X},
 439
 440         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 441                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 442                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 443                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 444                 RATE_IN_242X},
 445
 446         /* PRCM III - FAST */
 447         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 448                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 449                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 450                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 451                 RATE_IN_242X},
 452
 453         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 454                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 455                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 456                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 457                 RATE_IN_242X},
 458
 459         /* PRCM II - SLOW */
 460         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 461                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 462                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 463                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 464                 RATE_IN_242X},
 465
 466         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 467                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 468                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 469                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 470                 RATE_IN_242X},
 471
 472         /* PRCM III - SLOW */
 473         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 474                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 475                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 476                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 477                 RATE_IN_242X},
 478
 479         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 480                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 481                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 482                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 483                 RATE_IN_242X},
 484
 485         /* PRCM-VII (boot-bypass) */
 486         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 487                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 488                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 489                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 490                 RATE_IN_242X},
 491
 492         /* PRCM-VII (boot-bypass) */
 493         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 494                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 495                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 496                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 497                 RATE_IN_242X},
 498
 499         /* PRCM #3 - ratio2 (ES2) - FAST */
 500         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 501                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 502                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 504                 V24XX_SDRC_RFR_CTRL_110MHz,
 505                 RATE_IN_243X},
 506
 507         /* PRCM #5a - ratio1 - FAST */
 508         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 509                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 510                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 511                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 512                 V24XX_SDRC_RFR_CTRL_133MHz,
 513                 RATE_IN_243X},
 514
 515         /* PRCM #5b - ratio1 - FAST */
 516         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 517                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 518                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 519                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 520                 V24XX_SDRC_RFR_CTRL_100MHz,
 521                 RATE_IN_243X},
 522
 523         /* PRCM #3 - ratio2 (ES2) - SLOW */
 524         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 525                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 526                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 527                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 528                 V24XX_SDRC_RFR_CTRL_110MHz,
 529                 RATE_IN_243X},
 530
 531         /* PRCM #5a - ratio1 - SLOW */
 532         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 533                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 534                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 535                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 536                 V24XX_SDRC_RFR_CTRL_133MHz,
 537                 RATE_IN_243X},
 538
 539         /* PRCM #5b - ratio1 - SLOW*/
 540         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 541                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 542                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 543                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 544                 V24XX_SDRC_RFR_CTRL_100MHz,
 545                 RATE_IN_243X},
 546
 547         /* PRCM-boot/bypass */
 548         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 549                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 550                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 551                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 552                 V24XX_SDRC_RFR_CTRL_BYPASS,
 553                 RATE_IN_243X},
 554
 555         /* PRCM-boot/bypass */
 556         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 557                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 558                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 559                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 560                 V24XX_SDRC_RFR_CTRL_BYPASS,
 561                 RATE_IN_243X},
 562
 563         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 564 };
 565
 566 /*-------------------------------------------------------------------------
 567  * 24xx clock tree.
 568  *
 569  * NOTE:In many cases here we are assigning a 'default' parent. In many
 570  *      cases the parent is selectable. The get/set parent calls will also
 571  *      switch sources.
 572  *
 573  *      Many some clocks say always_enabled, but they can be auto idled for
 574  *      power savings. They will always be available upon clock request.
 575  *
 576  *      Several sources are given initial rates which may be wrong, this will
 577  *      be fixed up in the init func.
 578  *
 579  *      Things are broadly separated below by clock domains. It is
 580  *      noteworthy that most periferals have dependencies on multiple clock
 581  *      domains. Many get their interface clocks from the L4 domain, but get
 582  *      functional clocks from fixed sources or other core domain derived
 583  *      clocks.
 584  *-------------------------------------------------------------------------*/
 585
 586 /* Base external input clocks */
 587 static struct clk func_32k_ck = {
 588         .name           = "func_32k_ck",
 589         .rate           = 32000,
 590         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 591                                 RATE_FIXED | ALWAYS_ENABLED,
 592 };
 593
 594 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 595 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 596         .name           = "osc_ck",
 597         .rate           = 26000000,             /* fixed up in clock init */
 598         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 599                                 RATE_FIXED | RATE_PROPAGATES,
 600 };
 601
 602 /* With out modem likely 12MHz, with modem likely 13MHz */
 603 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 604         .name           = "sys_ck",             /* ~ ref_clk also */
 605         .parent         = &osc_ck,
 606         .rate           = 13000000,
 607         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 608                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 609         .rate_offset    = 6, /* sysclkdiv 1 or 2, already handled or no boot */
 610         .recalc         = &omap2_sys_clk_recalc,
 611 };
 612
 613 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 614         .name           = "alt_ck",
 615         .rate           = 54000000,
 616         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 617                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 618         .recalc         = &omap2_propagate_rate,
 619 };
 620
 621 /*
 622  * Analog domain root source clocks
 623  */
 624
 625 /* dpll_ck, is broken out in to special cases through clksel */
 626 static struct clk dpll_ck = {
 627         .name           = "dpll_ck",
 628         .parent         = &sys_ck,              /* Can be func_32k also */
 629         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 630                                 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
 631         .recalc         = &omap2_clksel_recalc,
 632 };
 633
 634 static struct clk apll96_ck = {
 635         .name           = "apll96_ck",
 636         .parent         = &sys_ck,
 637         .rate           = 96000000,
 638         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 639                                 RATE_FIXED | RATE_PROPAGATES,
 640         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 641         .enable_bit     = 0x2,
 642         .recalc         = &omap2_propagate_rate,
 643 };
 644
 645 static struct clk apll54_ck = {
 646         .name           = "apll54_ck",
 647         .parent         = &sys_ck,
 648         .rate           = 54000000,
 649         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 650                                 RATE_FIXED | RATE_PROPAGATES,
 651         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 652         .enable_bit     = 0x6,
 653         .recalc         = &omap2_propagate_rate,
 654 };
 655
 656 /*
 657  * PRCM digital base sources
 658  */
 659 static struct clk func_54m_ck = {
 660         .name           = "func_54m_ck",
 661         .parent         = &apll54_ck,   /* can also be alt_clk */
 662         .rate           = 54000000,
 663         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 664                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 665         .src_offset     = 5,
 666         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 667         .enable_bit     = 0xff,
 668         .recalc         = &omap2_propagate_rate,
 669 };
 670
 671 static struct clk core_ck = {
 672         .name           = "core_ck",
 673         .parent         = &dpll_ck,             /* can also be 32k */
 674         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 675                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 676         .recalc         = &omap2_propagate_rate,
 677 };
 678
 679 static struct clk sleep_ck = {          /* sys_clk or 32k */
 680         .name           = "sleep_ck",
 681         .parent         = &func_32k_ck,
 682         .rate           = 32000,
 683         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 684         .recalc         = &omap2_propagate_rate,
 685 };
 686
 687 static struct clk func_96m_ck = {
 688         .name           = "func_96m_ck",
 689         .parent         = &apll96_ck,
 690         .rate           = 96000000,
 691         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 692                                 RATE_FIXED | RATE_PROPAGATES,
 693         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 694         .enable_bit     = 0xff,
 695         .recalc         = &omap2_propagate_rate,
 696 };
 697
 698 static struct clk func_48m_ck = {
 699         .name           = "func_48m_ck",
 700         .parent         = &apll96_ck,    /* 96M or Alt */
 701         .rate           = 48000000,
 702         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 703                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 704         .src_offset     = 3,
 705         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 706         .enable_bit     = 0xff,
 707         .recalc         = &omap2_propagate_rate,
 708 };
 709
 710 static struct clk func_12m_ck = {
 711         .name           = "func_12m_ck",
 712         .parent         = &func_48m_ck,
 713         .rate           = 12000000,
 714         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 715                                 RATE_FIXED | RATE_PROPAGATES,
 716         .recalc         = &omap2_propagate_rate,
 717         .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
 718         .enable_bit     = 0xff,
 719 };
 720
 721 /* Secure timer, only available in secure mode */
 722 static struct clk wdt1_osc_ck = {
 723         .name           = "ck_wdt1_osc",
 724         .parent         = &osc_ck,
 725         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 726         .recalc         = &omap2_followparent_recalc,
 727 };
 728
 729 static struct clk sys_clkout = {
 730         .name           = "sys_clkout",
 731         .parent         = &func_54m_ck,
 732         .rate           = 54000000,
 733         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 734                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 735         .src_offset     = 0,
 736         .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
 737         .enable_bit     = 7,
 738         .rate_offset    = 3,
 739         .recalc         = &omap2_clksel_recalc,
 740 };
 741
 742 /* In 2430, new in 2420 ES2 */
 743 static struct clk sys_clkout2 = {
 744         .name           = "sys_clkout2",
 745         .parent         = &func_54m_ck,
 746         .rate           = 54000000,
 747         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 748                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 749         .src_offset     = 8,
 750         .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
 751         .enable_bit     = 15,
 752         .rate_offset    = 11,
 753         .recalc         = &omap2_clksel_recalc,
 754 };
 755
 756 static struct clk emul_ck = {
 757         .name           = "emul_ck",
 758         .parent         = &func_54m_ck,
 759         .flags          = CLOCK_IN_OMAP242X,
 760         .enable_reg     = (void __iomem *)&PRCM_CLKEMUL_CTRL,
 761         .enable_bit     = 0,
 762         .recalc         = &omap2_propagate_rate,
 763
 764 };
 765
 766 /*
 767  * MPU clock domain
 768  *      Clocks:
 769  *              MPU_FCLK, MPU_ICLK
 770  *              INT_M_FCLK, INT_M_I_CLK
 771  *
 772  * - Individual clocks are hardware managed.
 773  * - Base divider comes from: CM_CLKSEL_MPU
 774  *
 775  */
 776 static struct clk mpu_ck = {    /* Control cpu */
 777         .name           = "mpu_ck",
 778         .parent         = &core_ck,
 779         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
 780                                 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 781                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 782         .rate_offset    = 0,    /* bits 0-4 */
 783         .recalc         = &omap2_clksel_recalc,
 784 };
 785
 786 /*
 787  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 788  * Clocks:
 789  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 790  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 791  */
 792 static struct clk iva2_1_fck = {
 793         .name           = "iva2_1_fck",
 794         .parent         = &core_ck,
 795         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 796                                 DELAYED_APP | RATE_PROPAGATES |
 797                                 CONFIG_PARTICIPANT,
 798         .rate_offset    = 0,
 799         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
 800         .enable_bit     = 0,
 801         .recalc         = &omap2_clksel_recalc,
 802 };
 803
 804 static struct clk iva2_1_ick = {
 805         .name           = "iva2_1_ick",
 806         .parent         = &iva2_1_fck,
 807         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 808                                 DELAYED_APP | CONFIG_PARTICIPANT,
 809         .rate_offset    = 5,
 810         .recalc         = &omap2_clksel_recalc,
 811 };
 812
 813 /*
 814  * Won't be too specific here. The core clock comes into this block
 815  * it is divided then tee'ed. One branch goes directly to xyz enable
 816  * controls. The other branch gets further divided by 2 then possibly
 817  * routed into a synchronizer and out of clocks abc.
 818  */
 819 static struct clk dsp_fck = {
 820         .name           = "dsp_fck",
 821         .parent         = &core_ck,
 822         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 823                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
 824         .rate_offset    = 0,
 825         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
 826         .enable_bit     = 0,
 827         .recalc         = &omap2_clksel_recalc,
 828 };
 829
 830 static struct clk dsp_ick = {
 831         .name           = "dsp_ick",     /* apparently ipi and isp */
 832         .parent         = &dsp_fck,
 833         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 834                                 DELAYED_APP | CONFIG_PARTICIPANT,
 835         .rate_offset = 5,
 836         .enable_reg     = (void __iomem *)&CM_ICLKEN_DSP,
 837         .enable_bit     = 1,            /* for ipi */
 838         .recalc         = &omap2_clksel_recalc,
 839 };
 840
 841 static struct clk iva1_ifck = {
 842         .name           = "iva1_ifck",
 843         .parent         = &core_ck,
 844         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
 845                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
 846         .rate_offset= 8,
 847         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
 848         .enable_bit     = 10,
 849         .recalc         = &omap2_clksel_recalc,
 850 };
 851
 852 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 853 static struct clk iva1_mpu_int_ifck = {
 854         .name           = "iva1_mpu_int_ifck",
 855         .parent         = &iva1_ifck,
 856         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
 857         .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
 858         .enable_bit     = 8,
 859         .recalc         = &omap2_clksel_recalc,
 860 };
 861
 862 /*
 863  * L3 clock domain
 864  * L3 clocks are used for both interface and functional clocks to
 865  * multiple entities. Some of these clocks are completely managed
 866  * by hardware, and some others allow software control. Hardware
 867  * managed ones general are based on directly CLK_REQ signals and
 868  * various auto idle settings. The functional spec sets many of these
 869  * as 'tie-high' for their enables.
 870  *
 871  * I-CLOCKS:
 872  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 873  *      CAM, HS-USB.
 874  * F-CLOCK
 875  *      SSI.
 876  *
 877  * GPMC memories and SDRC have timing and clock sensitive registers which
 878  * may very well need notification when the clock changes. Currently for low
 879  * operating points, these are taken care of in sleep.S.
 880  */
 881 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 882         .name           = "core_l3_ck",
 883         .parent         = &core_ck,
 884         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 885                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 886                                 DELAYED_APP | CONFIG_PARTICIPANT |
 887                                 RATE_PROPAGATES,
 888         .rate_offset    = 0,
 889         .recalc         = &omap2_clksel_recalc,
 890 };
 891
 892 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 893         .name           = "usb_l4_ick",
 894         .parent         = &core_l3_ck,
 895         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 896                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
 897                                 CONFIG_PARTICIPANT,
 898         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
 899         .enable_bit     = 0,
 900         .rate_offset = 25,
 901         .recalc         = &omap2_clksel_recalc,
 902 };
 903
 904 /*
 905  * SSI is in L3 management domain, its direct parent is core not l3,
 906  * many core power domain entities are grouped into the L3 clock
 907  * domain.
 908  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
 909  *
 910  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 911  */
 912 static struct clk ssi_ssr_sst_fck = {
 913         .name           = "ssi_fck",
 914         .parent         = &core_ck,
 915         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 916                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 917         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,     /* bit 1 */
 918         .enable_bit     = 1,
 919         .rate_offset = 20,
 920         .recalc         = &omap2_clksel_recalc,
 921 };
 922
 923 /*
 924  * GFX clock domain
 925  *      Clocks:
 926  * GFX_FCLK, GFX_ICLK
 927  * GFX_CG1(2d), GFX_CG2(3d)
 928  *
 929  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 930  * The 2d and 3d clocks run at a hardware determined
 931  * divided value of fclk.
 932  *
 933  */
 934 static struct clk gfx_3d_fck = {
 935         .name           = "gfx_3d_fck",
 936         .parent         = &core_l3_ck,
 937         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 938                                 RATE_CKCTL | CM_GFX_SEL1,
 939         .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
 940         .enable_bit     = 2,
 941         .rate_offset= 0,
 942         .recalc         = &omap2_clksel_recalc,
 943 };
 944
 945 static struct clk gfx_2d_fck = {
 946         .name           = "gfx_2d_fck",
 947         .parent         = &core_l3_ck,
 948         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 949                                 RATE_CKCTL | CM_GFX_SEL1,
 950         .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
 951         .enable_bit     = 1,
 952         .rate_offset= 0,
 953         .recalc         = &omap2_clksel_recalc,
 954 };
 955
 956 static struct clk gfx_ick = {
 957         .name           = "gfx_ick",            /* From l3 */
 958         .parent         = &core_l3_ck,
 959         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 960                                 RATE_CKCTL,
 961         .enable_reg     = (void __iomem *)&CM_ICLKEN_GFX,       /* bit 0 */
 962         .enable_bit     = 0,
 963         .recalc         = &omap2_followparent_recalc,
 964 };
 965
 966 /*
 967  * Modem clock domain (2430)
 968  *      CLOCKS:
 969  *              MDM_OSC_CLK
 970  *              MDM_ICLK
 971  */
 972 static struct clk mdm_ick = {           /* used both as a ick and fck */
 973         .name           = "mdm_ick",
 974         .parent         = &core_ck,
 975         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
 976                                 DELAYED_APP | CONFIG_PARTICIPANT,
 977         .rate_offset    = 0,
 978         .enable_reg     = (void __iomem *)&CM_ICLKEN_MDM,
 979         .enable_bit     = 0,
 980         .recalc         = &omap2_clksel_recalc,
 981 };
 982
 983 static struct clk mdm_osc_ck = {
 984         .name           = "mdm_osc_ck",
 985         .rate           = 26000000,
 986         .parent         = &osc_ck,
 987         .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
 988         .enable_reg     = (void __iomem *)&CM_FCLKEN_MDM,
 989         .enable_bit     = 1,
 990         .recalc         = &omap2_followparent_recalc,
 991 };
 992
 993 /*
 994  * L4 clock management domain
 995  *
 996  * This domain contains lots of interface clocks from the L4 interface, some
 997  * functional clocks.   Fixed APLL functional source clocks are managed in
 998  * this domain.
 999  */
1000 static struct clk l4_ck = {             /* used both as an ick and fck */
1001         .name           = "l4_ck",
1002         .parent         = &core_l3_ck,
1003         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1004                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1005                                 DELAYED_APP | RATE_PROPAGATES,
1006         .rate_offset    = 5,
1007         .recalc         = &omap2_clksel_recalc,
1008 };
1009
1010 static struct clk ssi_l4_ick = {
1011         .name           = "ssi_l4_ick",
1012         .parent         = &l4_ck,
1013         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1014         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,     /* bit 1 */
1015         .enable_bit     = 1,
1016         .recalc         = &omap2_followparent_recalc,
1017 };
1018
1019 /*
1020  * DSS clock domain
1021  * CLOCKs:
1022  * DSS_L4_ICLK, DSS_L3_ICLK,
1023  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1024  *
1025  * DSS is both initiator and target.
1026  */
1027 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1028         .name           = "dss_ick",
1029         .parent         = &l4_ck,       /* really both l3 and l4 */
1030         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
1031         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1032         .enable_bit     = 0,
1033         .recalc         = &omap2_followparent_recalc,
1034 };
1035
1036 static struct clk dss1_fck = {
1037         .name           = "dss1_fck",
1038         .parent         = &core_ck,             /* Core or sys */
1039         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1040                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1041         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1042         .enable_bit     = 0,
1043         .rate_offset    = 8,
1044         .src_offset     = 8,
1045         .recalc         = &omap2_clksel_recalc,
1046 };
1047
1048 static struct clk dss2_fck = {          /* Alt clk used in power management */
1049         .name           = "dss2_fck",
1050         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1051         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1052                                 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1053                                 DELAYED_APP,
1054         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1055         .enable_bit     = 1,
1056         .src_offset     = 13,
1057         .recalc         = &omap2_followparent_recalc,
1058 };
1059
1060 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1061         .name           = "dss_54m_fck",        /* 54m tv clk */
1062         .parent         = &func_54m_ck,
1063         .rate           = 54000000,
1064         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1065                                 RATE_FIXED | RATE_PROPAGATES,
1066         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1067         .enable_bit     = 2,
1068         .recalc         = &omap2_propagate_rate,
1069 };
1070
1071 /*
1072  * CORE power domain ICLK & FCLK defines.
1073  * Many of the these can have more than one possible parent. Entries
1074  * here will likely have an L4 interface parent, and may have multiple
1075  * functional clock parents.
1076  */
1077 static struct clk gpt1_ick = {
1078         .name           = "gpt1_ick",
1079         .parent         = &l4_ck,
1080         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1081         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,      /* Bit0 */
1082         .enable_bit     = 0,
1083         .recalc         = &omap2_followparent_recalc,
1084 };
1085
1086 static struct clk gpt1_fck = {
1087         .name           = "gpt1_fck",
1088         .parent         = &func_32k_ck,
1089         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1090                                 CM_WKUP_SEL1,
1091         .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,      /* Bit0 */
1092         .enable_bit     = 0,
1093         .src_offset     = 0,
1094         .recalc         = &omap2_followparent_recalc,
1095 };
1096
1097 static struct clk gpt2_ick = {
1098         .name           = "gpt2_ick",
1099         .parent         = &l4_ck,
1100         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1101         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit4 */
1102         .enable_bit     = 4,
1103         .recalc         = &omap2_followparent_recalc,
1104 };
1105
1106 static struct clk gpt2_fck = {
1107         .name           = "gpt2_fck",
1108         .parent         = &func_32k_ck,
1109         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1110                                 CM_CORE_SEL2,
1111         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1112         .enable_bit     = 4,
1113         .src_offset     = 2,
1114         .recalc         = &omap2_followparent_recalc,
1115 };
1116
1117 static struct clk gpt3_ick = {
1118         .name           = "gpt3_ick",
1119         .parent         = &l4_ck,
1120         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1121         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit5 */
1122         .enable_bit     = 5,
1123         .recalc         = &omap2_followparent_recalc,
1124 };
1125
1126 static struct clk gpt3_fck = {
1127         .name           = "gpt3_fck",
1128         .parent         = &func_32k_ck,
1129         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1130                                 CM_CORE_SEL2,
1131         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1132         .enable_bit     = 5,
1133         .src_offset     = 4,
1134         .recalc         = &omap2_followparent_recalc,
1135 };
1136
1137 static struct clk gpt4_ick = {
1138         .name           = "gpt4_ick",
1139         .parent         = &l4_ck,
1140         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1141         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit6 */
1142         .enable_bit     = 6,
1143         .recalc         = &omap2_followparent_recalc,
1144 };
1145
1146 static struct clk gpt4_fck = {
1147         .name           = "gpt4_fck",
1148         .parent         = &func_32k_ck,
1149         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1150                                 CM_CORE_SEL2,
1151         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1152         .enable_bit     = 6,
1153         .src_offset     = 6,
1154         .recalc         = &omap2_followparent_recalc,
1155 };
1156
1157 static struct clk gpt5_ick = {
1158         .name           = "gpt5_ick",
1159         .parent         = &l4_ck,
1160         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1161         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* Bit7 */
1162         .enable_bit     = 7,
1163         .recalc         = &omap2_followparent_recalc,
1164 };
1165
1166 static struct clk gpt5_fck = {
1167         .name           = "gpt5_fck",
1168         .parent         = &func_32k_ck,
1169         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1170                                 CM_CORE_SEL2,
1171         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1172         .enable_bit     = 7,
1173         .src_offset     = 8,
1174         .recalc         = &omap2_followparent_recalc,
1175 };
1176
1177 static struct clk gpt6_ick = {
1178         .name           = "gpt6_ick",
1179         .parent         = &l4_ck,
1180         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1181         .enable_bit     = 8,
1182         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit8 */
1183         .recalc         = &omap2_followparent_recalc,
1184 };
1185
1186 static struct clk gpt6_fck = {
1187         .name           = "gpt6_fck",
1188         .parent         = &func_32k_ck,
1189         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1190                                 CM_CORE_SEL2,
1191         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1192         .enable_bit     = 8,
1193         .src_offset     = 10,
1194         .recalc         = &omap2_followparent_recalc,
1195 };
1196
1197 static struct clk gpt7_ick = {
1198         .name           = "gpt7_ick",
1199         .parent         = &l4_ck,
1200         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1201         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit9 */
1202         .enable_bit     = 9,
1203         .recalc         = &omap2_followparent_recalc,
1204 };
1205
1206 static struct clk gpt7_fck = {
1207         .name           = "gpt7_fck",
1208         .parent         = &func_32k_ck,
1209         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1210                                 CM_CORE_SEL2,
1211         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1212         .enable_bit     = 9,
1213         .src_offset     = 12,
1214         .recalc         = &omap2_followparent_recalc,
1215 };
1216
1217 static struct clk gpt8_ick = {
1218         .name           = "gpt8_ick",
1219         .parent         = &l4_ck,
1220         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1221         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit10 */
1222         .enable_bit     = 10,
1223         .recalc         = &omap2_followparent_recalc,
1224 };
1225
1226 static struct clk gpt8_fck = {
1227         .name           = "gpt8_fck",
1228         .parent         = &func_32k_ck,
1229         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1230                                 CM_CORE_SEL2,
1231         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1232         .enable_bit     = 10,
1233         .src_offset     = 14,
1234         .recalc         = &omap2_followparent_recalc,
1235 };
1236
1237 static struct clk gpt9_ick = {
1238         .name           = "gpt9_ick",
1239         .parent         = &l4_ck,
1240         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1241         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1242         .enable_bit     = 11,
1243         .recalc         = &omap2_followparent_recalc,
1244 };
1245
1246 static struct clk gpt9_fck = {
1247         .name           = "gpt9_fck",
1248         .parent         = &func_32k_ck,
1249         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1250                                         CM_CORE_SEL2,
1251         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1252         .enable_bit     = 11,
1253         .src_offset     = 16,
1254         .recalc         = &omap2_followparent_recalc,
1255 };
1256
1257 static struct clk gpt10_ick = {
1258         .name           = "gpt10_ick",
1259         .parent         = &l4_ck,
1260         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1261         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1262         .enable_bit     = 12,
1263         .recalc         = &omap2_followparent_recalc,
1264 };
1265
1266 static struct clk gpt10_fck = {
1267         .name           = "gpt10_fck",
1268         .parent         = &func_32k_ck,
1269         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1270                                         CM_CORE_SEL2,
1271         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1272         .enable_bit     = 12,
1273         .src_offset     = 18,
1274         .recalc         = &omap2_followparent_recalc,
1275 };
1276
1277 static struct clk gpt11_ick = {
1278         .name           = "gpt11_ick",
1279         .parent         = &l4_ck,
1280         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1281         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1282         .enable_bit     = 13,
1283         .recalc         = &omap2_followparent_recalc,
1284 };
1285
1286 static struct clk gpt11_fck = {
1287         .name           = "gpt11_fck",
1288         .parent         = &func_32k_ck,
1289         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1290                                         CM_CORE_SEL2,
1291         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1292         .enable_bit     = 13,
1293         .src_offset     = 20,
1294         .recalc         = &omap2_followparent_recalc,
1295 };
1296
1297 static struct clk gpt12_ick = {
1298         .name           = "gpt12_ick",
1299         .parent         = &l4_ck,
1300         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1301         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit14 */
1302         .enable_bit     = 14,
1303         .recalc         = &omap2_followparent_recalc,
1304 };
1305
1306 static struct clk gpt12_fck = {
1307         .name           = "gpt12_fck",
1308         .parent         = &func_32k_ck,
1309         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1310                                         CM_CORE_SEL2,
1311         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1312         .enable_bit     = 14,
1313         .src_offset     = 22,
1314         .recalc         = &omap2_followparent_recalc,
1315 };
1316
1317 static struct clk mcbsp1_ick = {
1318         .name           = "mcbsp1_ick",
1319         .parent         = &l4_ck,
1320         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1321         .enable_bit     = 15,
1322         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit16 */
1323         .recalc         = &omap2_followparent_recalc,
1324 };
1325
1326 static struct clk mcbsp1_fck = {
1327         .name           = "mcbsp1_fck",
1328         .parent         = &func_96m_ck,
1329         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1330         .enable_bit     = 15,
1331         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1332         .recalc         = &omap2_followparent_recalc,
1333 };
1334
1335 static struct clk mcbsp2_ick = {
1336         .name           = "mcbsp2_ick",
1337         .parent         = &l4_ck,
1338         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1339         .enable_bit     = 16,
1340         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1341         .recalc         = &omap2_followparent_recalc,
1342 };
1343
1344 static struct clk mcbsp2_fck = {
1345         .name           = "mcbsp2_fck",
1346         .parent         = &func_96m_ck,
1347         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1348         .enable_bit     = 16,
1349         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1350         .recalc         = &omap2_followparent_recalc,
1351 };
1352
1353 static struct clk mcbsp3_ick = {
1354         .name           = "mcbsp3_ick",
1355         .parent         = &l4_ck,
1356         .flags          = CLOCK_IN_OMAP243X,
1357         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1358         .enable_bit     = 3,
1359         .recalc         = &omap2_followparent_recalc,
1360 };
1361
1362 static struct clk mcbsp3_fck = {
1363         .name           = "mcbsp3_fck",
1364         .parent         = &func_96m_ck,
1365         .flags          = CLOCK_IN_OMAP243X,
1366         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1367         .enable_bit     = 3,
1368         .recalc         = &omap2_followparent_recalc,
1369 };
1370
1371 static struct clk mcbsp4_ick = {
1372         .name           = "mcbsp4_ick",
1373         .parent         = &l4_ck,
1374         .flags          = CLOCK_IN_OMAP243X,
1375         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1376         .enable_bit     = 4,
1377         .recalc         = &omap2_followparent_recalc,
1378 };
1379
1380 static struct clk mcbsp4_fck = {
1381         .name           = "mcbsp4_fck",
1382         .parent         = &func_96m_ck,
1383         .flags          = CLOCK_IN_OMAP243X,
1384         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1385         .enable_bit     = 4,
1386         .recalc         = &omap2_followparent_recalc,
1387 };
1388
1389 static struct clk mcbsp5_ick = {
1390         .name           = "mcbsp5_ick",
1391         .parent         = &l4_ck,
1392         .flags          = CLOCK_IN_OMAP243X,
1393         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1394         .enable_bit     = 5,
1395         .recalc         = &omap2_followparent_recalc,
1396 };
1397
1398 static struct clk mcbsp5_fck = {
1399         .name           = "mcbsp5_fck",
1400         .parent         = &func_96m_ck,
1401         .flags          = CLOCK_IN_OMAP243X,
1402         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1403         .enable_bit     = 5,
1404         .recalc         = &omap2_followparent_recalc,
1405 };
1406
1407 static struct clk mcspi1_ick = {
1408         .name           = "mcspi_ick",
1409         .id             = 1,
1410         .parent         = &l4_ck,
1411         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1412         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1413         .enable_bit     = 17,
1414         .recalc         = &omap2_followparent_recalc,
1415 };
1416
1417 static struct clk mcspi1_fck = {
1418         .name           = "mcspi_fck",
1419         .id             = 1,
1420         .parent         = &func_48m_ck,
1421         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1422         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1423         .enable_bit     = 17,
1424         .recalc         = &omap2_followparent_recalc,
1425 };
1426
1427 static struct clk mcspi2_ick = {
1428         .name           = "mcspi_ick",
1429         .id             = 2,
1430         .parent         = &l4_ck,
1431         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1432         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1433         .enable_bit     = 18,
1434         .recalc         = &omap2_followparent_recalc,
1435 };
1436
1437 static struct clk mcspi2_fck = {
1438         .name           = "mcspi_fck",
1439         .id             = 2,
1440         .parent         = &func_48m_ck,
1441         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1442         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1443         .enable_bit     = 18,
1444         .recalc         = &omap2_followparent_recalc,
1445 };
1446
1447 static struct clk mcspi3_ick = {
1448         .name           = "mcspi_ick",
1449         .id             = 3,
1450         .parent         = &l4_ck,
1451         .flags          = CLOCK_IN_OMAP243X,
1452         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1453         .enable_bit     = 9,
1454         .recalc         = &omap2_followparent_recalc,
1455 };
1456
1457 static struct clk mcspi3_fck = {
1458         .name           = "mcspi_fck",
1459         .id             = 3,
1460         .parent         = &func_48m_ck,
1461         .flags          = CLOCK_IN_OMAP243X,
1462         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1463         .enable_bit     = 9,
1464         .recalc         = &omap2_followparent_recalc,
1465 };
1466
1467 static struct clk uart1_ick = {
1468         .name           = "uart1_ick",
1469         .parent         = &l4_ck,
1470         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1471         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1472         .enable_bit     = 21,
1473         .recalc         = &omap2_followparent_recalc,
1474 };
1475
1476 static struct clk uart1_fck = {
1477         .name           = "uart1_fck",
1478         .parent         = &func_48m_ck,
1479         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1480         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1481         .enable_bit     = 21,
1482         .recalc         = &omap2_followparent_recalc,
1483 };
1484
1485 static struct clk uart2_ick = {
1486         .name           = "uart2_ick",
1487         .parent         = &l4_ck,
1488         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1489         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1490         .enable_bit     = 22,
1491         .recalc         = &omap2_followparent_recalc,
1492 };
1493
1494 static struct clk uart2_fck = {
1495         .name           = "uart2_fck",
1496         .parent         = &func_48m_ck,
1497         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1498         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1499         .enable_bit     = 22,
1500         .recalc         = &omap2_followparent_recalc,
1501 };
1502
1503 static struct clk uart3_ick = {
1504         .name           = "uart3_ick",
1505         .parent         = &l4_ck,
1506         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1507         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1508         .enable_bit     = 2,
1509         .recalc         = &omap2_followparent_recalc,
1510 };
1511
1512 static struct clk uart3_fck = {
1513         .name           = "uart3_fck",
1514         .parent         = &func_48m_ck,
1515         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1516         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1517         .enable_bit     = 2,
1518         .recalc         = &omap2_followparent_recalc,
1519 };
1520
1521 static struct clk gpios_ick = {
1522         .name           = "gpios_ick",
1523         .parent         = &l4_ck,
1524         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1525         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1526         .enable_bit     = 2,
1527         .recalc         = &omap2_followparent_recalc,
1528 };
1529
1530 static struct clk gpios_fck = {
1531         .name           = "gpios_fck",
1532         .parent         = &func_32k_ck,
1533         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1534         .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
1535         .enable_bit     = 2,
1536         .recalc         = &omap2_followparent_recalc,
1537 };
1538
1539 static struct clk mpu_wdt_ick = {
1540         .name           = "mpu_wdt_ick",
1541         .parent         = &l4_ck,
1542         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1543         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1544         .enable_bit     = 3,
1545         .recalc         = &omap2_followparent_recalc,
1546 };
1547
1548 static struct clk mpu_wdt_fck = {
1549         .name           = "mpu_wdt_fck",
1550         .parent         = &func_32k_ck,
1551         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1552         .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
1553         .enable_bit     = 3,
1554         .recalc         = &omap2_followparent_recalc,
1555 };
1556
1557 static struct clk sync_32k_ick = {
1558         .name           = "sync_32k_ick",
1559         .parent         = &l4_ck,
1560         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1561         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1562         .enable_bit     = 1,
1563         .recalc         = &omap2_followparent_recalc,
1564 };
1565 static struct clk wdt1_ick = {
1566         .name           = "wdt1_ick",
1567         .parent         = &l4_ck,
1568         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1569         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1570         .enable_bit     = 4,
1571         .recalc         = &omap2_followparent_recalc,
1572 };
1573 static struct clk omapctrl_ick = {
1574         .name           = "omapctrl_ick",
1575         .parent         = &l4_ck,
1576         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1577         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1578         .enable_bit     = 5,
1579         .recalc         = &omap2_followparent_recalc,
1580 };
1581 static struct clk icr_ick = {
1582         .name           = "icr_ick",
1583         .parent         = &l4_ck,
1584         .flags          = CLOCK_IN_OMAP243X,
1585         .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
1586         .enable_bit     = 6,
1587         .recalc         = &omap2_followparent_recalc,
1588 };
1589
1590 static struct clk cam_ick = {
1591         .name           = "cam_ick",
1592         .parent         = &l4_ck,
1593         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1594         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1595         .enable_bit     = 31,
1596         .recalc         = &omap2_followparent_recalc,
1597 };
1598
1599 static struct clk cam_fck = {
1600         .name           = "cam_fck",
1601         .parent         = &func_96m_ck,
1602         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1603         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1604         .enable_bit     = 31,
1605         .recalc         = &omap2_followparent_recalc,
1606 };
1607
1608 static struct clk mailboxes_ick = {
1609         .name           = "mailboxes_ick",
1610         .parent         = &l4_ck,
1611         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1612         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1613         .enable_bit     = 30,
1614         .recalc         = &omap2_followparent_recalc,
1615 };
1616
1617 static struct clk wdt4_ick = {
1618         .name           = "wdt4_ick",
1619         .parent         = &l4_ck,
1620         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1622         .enable_bit     = 29,
1623         .recalc         = &omap2_followparent_recalc,
1624 };
1625
1626 static struct clk wdt4_fck = {
1627         .name           = "wdt4_fck",
1628         .parent         = &func_32k_ck,
1629         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1630         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1631         .enable_bit     = 29,
1632         .recalc         = &omap2_followparent_recalc,
1633 };
1634
1635 static struct clk wdt3_ick = {
1636         .name           = "wdt3_ick",
1637         .parent         = &l4_ck,
1638         .flags          = CLOCK_IN_OMAP242X,
1639         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1640         .enable_bit     = 28,
1641         .recalc         = &omap2_followparent_recalc,
1642 };
1643
1644 static struct clk wdt3_fck = {
1645         .name           = "wdt3_fck",
1646         .parent         = &func_32k_ck,
1647         .flags          = CLOCK_IN_OMAP242X,
1648         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1649         .enable_bit     = 28,
1650         .recalc         = &omap2_followparent_recalc,
1651 };
1652
1653 static struct clk mspro_ick = {
1654         .name           = "mspro_ick",
1655         .parent         = &l4_ck,
1656         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1657         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1658         .enable_bit     = 27,
1659         .recalc         = &omap2_followparent_recalc,
1660 };
1661
1662 static struct clk mspro_fck = {
1663         .name           = "mspro_fck",
1664         .parent         = &func_96m_ck,
1665         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1666         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1667         .enable_bit     = 27,
1668         .recalc         = &omap2_followparent_recalc,
1669 };
1670
1671 static struct clk mmc_ick = {
1672         .name           = "mmc_ick",
1673         .parent         = &l4_ck,
1674         .flags          = CLOCK_IN_OMAP242X,
1675         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1676         .enable_bit     = 26,
1677         .recalc         = &omap2_followparent_recalc,
1678 };
1679
1680 static struct clk mmc_fck = {
1681         .name           = "mmc_fck",
1682         .parent         = &func_96m_ck,
1683         .flags          = CLOCK_IN_OMAP242X,
1684         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1685         .enable_bit     = 26,
1686         .recalc         = &omap2_followparent_recalc,
1687 };
1688
1689 static struct clk fac_ick = {
1690         .name           = "fac_ick",
1691         .parent         = &l4_ck,
1692         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1693         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1694         .enable_bit     = 25,
1695         .recalc         = &omap2_followparent_recalc,
1696 };
1697
1698 static struct clk fac_fck = {
1699         .name           = "fac_fck",
1700         .parent         = &func_12m_ck,
1701         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1703         .enable_bit     = 25,
1704         .recalc         = &omap2_followparent_recalc,
1705 };
1706
1707 static struct clk eac_ick = {
1708         .name           = "eac_ick",
1709         .parent         = &l4_ck,
1710         .flags          = CLOCK_IN_OMAP242X,
1711         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1712         .enable_bit     = 24,
1713         .recalc         = &omap2_followparent_recalc,
1714 };
1715
1716 static struct clk eac_fck = {
1717         .name           = "eac_fck",
1718         .parent         = &func_96m_ck,
1719         .flags          = CLOCK_IN_OMAP242X,
1720         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1721         .enable_bit     = 24,
1722         .recalc         = &omap2_followparent_recalc,
1723 };
1724
1725 static struct clk hdq_ick = {
1726         .name           = "hdq_ick",
1727         .parent         = &l4_ck,
1728         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1729         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1730         .enable_bit     = 23,
1731         .recalc         = &omap2_followparent_recalc,
1732 };
1733
1734 static struct clk hdq_fck = {
1735         .name           = "hdq_fck",
1736         .parent         = &func_12m_ck,
1737         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1738         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1739         .enable_bit     = 23,
1740         .recalc         = &omap2_followparent_recalc,
1741 };
1742
1743 static struct clk i2c2_ick = {
1744         .name           = "i2c_ick",
1745         .id             = 2,
1746         .parent         = &l4_ck,
1747         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1748         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1749         .enable_bit     = 20,
1750         .recalc         = &omap2_followparent_recalc,
1751 };
1752
1753 static struct clk i2c2_fck = {
1754         .name           = "i2c_fck",
1755         .id             = 2,
1756         .parent         = &func_12m_ck,
1757         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1758         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1759         .enable_bit     = 20,
1760         .recalc         = &omap2_followparent_recalc,
1761 };
1762
1763 static struct clk i2chs2_fck = {
1764         .name           = "i2chs2_fck",
1765         .parent         = &func_96m_ck,
1766         .flags          = CLOCK_IN_OMAP243X,
1767         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1768         .enable_bit     = 20,
1769         .recalc         = &omap2_followparent_recalc,
1770 };
1771
1772 static struct clk i2c1_ick = {
1773         .name           = "i2c_ick",
1774         .id             = 1,
1775         .parent         = &l4_ck,
1776         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1777         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1778         .enable_bit     = 19,
1779         .recalc         = &omap2_followparent_recalc,
1780 };
1781
1782 static struct clk i2c1_fck = {
1783         .name           = "i2c_fck",
1784         .id             = 1,
1785         .parent         = &func_12m_ck,
1786         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1787         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1788         .enable_bit     = 19,
1789         .recalc         = &omap2_followparent_recalc,
1790 };
1791
1792 static struct clk i2chs1_fck = {
1793         .name           = "i2chs1_fck",
1794         .parent         = &func_96m_ck,
1795         .flags          = CLOCK_IN_OMAP243X,
1796         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1797         .enable_bit     = 19,
1798         .recalc         = &omap2_followparent_recalc,
1799 };
1800
1801 static struct clk vlynq_ick = {
1802         .name           = "vlynq_ick",
1803         .parent         = &core_l3_ck,
1804         .flags          = CLOCK_IN_OMAP242X,
1805         .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
1806         .enable_bit     = 3,
1807         .recalc         = &omap2_followparent_recalc,
1808 };
1809
1810 static struct clk vlynq_fck = {
1811         .name           = "vlynq_fck",
1812         .parent         = &func_96m_ck,
1813         .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1814         .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
1815         .enable_bit     = 3,
1816         .src_offset     = 15,
1817         .recalc         = &omap2_followparent_recalc,
1818 };
1819
1820 static struct clk sdrc_ick = {
1821         .name           = "sdrc_ick",
1822         .parent         = &l4_ck,
1823         .flags          = CLOCK_IN_OMAP243X,
1824         .enable_reg     = (void __iomem *)&CM_ICLKEN3_CORE,
1825         .enable_bit     = 2,
1826         .recalc         = &omap2_followparent_recalc,
1827 };
1828
1829 static struct clk des_ick = {
1830         .name           = "des_ick",
1831         .parent         = &l4_ck,
1832         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1833         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1834         .enable_bit     = 0,
1835         .recalc         = &omap2_followparent_recalc,
1836 };
1837
1838 static struct clk sha_ick = {
1839         .name           = "sha_ick",
1840         .parent         = &l4_ck,
1841         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1842         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1843         .enable_bit     = 1,
1844         .recalc         = &omap2_followparent_recalc,
1845 };
1846
1847 static struct clk rng_ick = {
1848         .name           = "rng_ick",
1849         .parent         = &l4_ck,
1850         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1851         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1852         .enable_bit     = 2,
1853         .recalc         = &omap2_followparent_recalc,
1854 };
1855
1856 static struct clk aes_ick = {
1857         .name           = "aes_ick",
1858         .parent         = &l4_ck,
1859         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1860         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1861         .enable_bit     = 3,
1862         .recalc         = &omap2_followparent_recalc,
1863 };
1864
1865 static struct clk pka_ick = {
1866         .name           = "pka_ick",
1867         .parent         = &l4_ck,
1868         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1869         .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
1870         .enable_bit     = 4,
1871         .recalc         = &omap2_followparent_recalc,
1872 };
1873
1874 static struct clk usb_fck = {
1875         .name           = "usb_fck",
1876         .parent         = &func_48m_ck,
1877         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1878         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1879         .enable_bit     = 0,
1880         .recalc         = &omap2_followparent_recalc,
1881 };
1882
1883 static struct clk usbhs_ick = {
1884         .name           = "usbhs_ick",
1885         .parent         = &core_l3_ck,
1886         .flags          = CLOCK_IN_OMAP243X,
1887         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1888         .enable_bit     = 6,
1889         .recalc         = &omap2_followparent_recalc,
1890 };
1891
1892 static struct clk mmchs1_ick = {
1893         .name           = "mmchs1_ick",
1894         .parent         = &l4_ck,
1895         .flags          = CLOCK_IN_OMAP243X,
1896         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1897         .enable_bit     = 7,
1898         .recalc         = &omap2_followparent_recalc,
1899 };
1900
1901 static struct clk mmchs1_fck = {
1902         .name           = "mmchs1_fck",
1903         .parent         = &func_96m_ck,
1904         .flags          = CLOCK_IN_OMAP243X,
1905         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1906         .enable_bit     = 7,
1907         .recalc         = &omap2_followparent_recalc,
1908 };
1909
1910 static struct clk mmchs2_ick = {
1911         .name           = "mmchs2_ick",
1912         .parent         = &l4_ck,
1913         .flags          = CLOCK_IN_OMAP243X,
1914         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1915         .enable_bit     = 8,
1916         .recalc         = &omap2_followparent_recalc,
1917 };
1918
1919 static struct clk mmchs2_fck = {
1920         .name           = "mmchs2_fck",
1921         .parent         = &func_96m_ck,
1922         .flags          = CLOCK_IN_OMAP243X,
1923         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1924         .enable_bit     = 8,
1925         .recalc         = &omap2_followparent_recalc,
1926 };
1927
1928 static struct clk gpio5_ick = {
1929         .name           = "gpio5_ick",
1930         .parent         = &l4_ck,
1931         .flags          = CLOCK_IN_OMAP243X,
1932         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1933         .enable_bit     = 10,
1934         .recalc         = &omap2_followparent_recalc,
1935 };
1936
1937 static struct clk gpio5_fck = {
1938         .name           = "gpio5_fck",
1939         .parent         = &func_32k_ck,
1940         .flags          = CLOCK_IN_OMAP243X,
1941         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1942         .enable_bit     = 10,
1943         .recalc         = &omap2_followparent_recalc,
1944 };
1945
1946 static struct clk mdm_intc_ick = {
1947         .name           = "mdm_intc_ick",
1948         .parent         = &l4_ck,
1949         .flags          = CLOCK_IN_OMAP243X,
1950         .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
1951         .enable_bit     = 11,
1952         .recalc         = &omap2_followparent_recalc,
1953 };
1954
1955 static struct clk mmchsdb1_fck = {
1956         .name           = "mmchsdb1_fck",
1957         .parent         = &func_32k_ck,
1958         .flags          = CLOCK_IN_OMAP243X,
1959         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1960         .enable_bit     = 16,
1961         .recalc         = &omap2_followparent_recalc,
1962 };
1963
1964 static struct clk mmchsdb2_fck = {
1965         .name           = "mmchsdb2_fck",
1966         .parent         = &func_32k_ck,
1967         .flags          = CLOCK_IN_OMAP243X,
1968         .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
1969         .enable_bit     = 17,
1970         .recalc         = &omap2_followparent_recalc,
1971 };
1972
1973 /*
1974  * This clock is a composite clock which does entire set changes then
1975  * forces a rebalance. It keys on the MPU speed, but it really could
1976  * be any key speed part of a set in the rate table.
1977  *
1978  * to really change a set, you need memory table sets which get changed
1979  * in sram, pre-notifiers & post notifiers, changing the top set, without
1980  * having low level display recalc's won't work... this is why dpm notifiers
1981  * work, isr's off, walk a list of clocks already _off_ and not messing with
1982  * the bus.
1983  *
1984  * This clock should have no parent. It embodies the entire upper level
1985  * active set. A parent will mess up some of the init also.
1986  */
1987 static struct clk virt_prcm_set = {
1988         .name           = "virt_prcm_set",
1989         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1990                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1991         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1992         .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
1993         .set_rate       = &omap2_select_table_rate,
1994         .round_rate     = &omap2_round_to_table_rate,
1995 };
1996
1997 static struct clk *onchip_clks[] = {
1998         /* external root sources */
1999         &func_32k_ck,
2000         &osc_ck,
2001         &sys_ck,
2002         &alt_ck,
2003         /* internal analog sources */
2004         &dpll_ck,
2005         &apll96_ck,
2006         &apll54_ck,
2007         /* internal prcm root sources */
2008         &func_54m_ck,
2009         &core_ck,
2010         &sleep_ck,
2011         &func_96m_ck,
2012         &func_48m_ck,
2013         &func_12m_ck,
2014         &wdt1_osc_ck,
2015         &sys_clkout,
2016         &sys_clkout2,
2017         &emul_ck,
2018         /* mpu domain clocks */
2019         &mpu_ck,
2020         /* dsp domain clocks */
2021         &iva2_1_fck,            /* 2430 */
2022         &iva2_1_ick,
2023         &dsp_ick,               /* 2420 */
2024         &dsp_fck,
2025         &iva1_ifck,
2026         &iva1_mpu_int_ifck,
2027         /* GFX domain clocks */
2028         &gfx_3d_fck,
2029         &gfx_2d_fck,
2030         &gfx_ick,
2031         /* Modem domain clocks */
2032         &mdm_ick,
2033         &mdm_osc_ck,
2034         /* DSS domain clocks */
2035         &dss_ick,
2036         &dss1_fck,
2037         &dss2_fck,
2038         &dss_54m_fck,
2039         /* L3 domain clocks */
2040         &core_l3_ck,
2041         &ssi_ssr_sst_fck,
2042         &usb_l4_ick,
2043         /* L4 domain clocks */
2044         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2045         &ssi_l4_ick,
2046         /* virtual meta-group clock */
2047         &virt_prcm_set,
2048         /* general l4 interface ck, multi-parent functional clk */
2049         &gpt1_ick,
2050         &gpt1_fck,
2051         &gpt2_ick,
2052         &gpt2_fck,
2053         &gpt3_ick,
2054         &gpt3_fck,
2055         &gpt4_ick,
2056         &gpt4_fck,
2057         &gpt5_ick,
2058         &gpt5_fck,
2059         &gpt6_ick,
2060         &gpt6_fck,
2061         &gpt7_ick,
2062         &gpt7_fck,
2063         &gpt8_ick,
2064         &gpt8_fck,
2065         &gpt9_ick,
2066         &gpt9_fck,
2067         &gpt10_ick,
2068         &gpt10_fck,
2069         &gpt11_ick,
2070         &gpt11_fck,
2071         &gpt12_ick,
2072         &gpt12_fck,
2073         &mcbsp1_ick,
2074         &mcbsp1_fck,
2075         &mcbsp2_ick,
2076         &mcbsp2_fck,
2077         &mcbsp3_ick,
2078         &mcbsp3_fck,
2079         &mcbsp4_ick,
2080         &mcbsp4_fck,
2081         &mcbsp5_ick,
2082         &mcbsp5_fck,
2083         &mcspi1_ick,
2084         &mcspi1_fck,
2085         &mcspi2_ick,
2086         &mcspi2_fck,
2087         &mcspi3_ick,
2088         &mcspi3_fck,
2089         &uart1_ick,
2090         &uart1_fck,
2091         &uart2_ick,
2092         &uart2_fck,
2093         &uart3_ick,
2094         &uart3_fck,
2095         &gpios_ick,
2096         &gpios_fck,
2097         &mpu_wdt_ick,
2098         &mpu_wdt_fck,
2099         &sync_32k_ick,
2100         &wdt1_ick,
2101         &omapctrl_ick,
2102         &icr_ick,
2103         &cam_fck,
2104         &cam_ick,
2105         &mailboxes_ick,
2106         &wdt4_ick,
2107         &wdt4_fck,
2108         &wdt3_ick,
2109         &wdt3_fck,
2110         &mspro_ick,
2111         &mspro_fck,
2112         &mmc_ick,
2113         &mmc_fck,
2114         &fac_ick,
2115         &fac_fck,
2116         &eac_ick,
2117         &eac_fck,
2118         &hdq_ick,
2119         &hdq_fck,
2120         &i2c1_ick,
2121         &i2c1_fck,
2122         &i2chs1_fck,
2123         &i2c2_ick,
2124         &i2c2_fck,
2125         &i2chs2_fck,
2126         &vlynq_ick,
2127         &vlynq_fck,
2128         &sdrc_ick,
2129         &des_ick,
2130         &sha_ick,
2131         &rng_ick,
2132         &aes_ick,
2133         &pka_ick,
2134         &usb_fck,
2135         &usbhs_ick,
2136         &mmchs1_ick,
2137         &mmchs1_fck,
2138         &mmchs2_ick,
2139         &mmchs2_fck,
2140         &gpio5_ick,
2141         &gpio5_fck,
2142         &mdm_intc_ick,
2143         &mmchsdb1_fck,
2144         &mmchsdb2_fck,
2145 };
2146
2147 #endif