arch/arm/mach-omap2/clock24xx.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Cleaned up and modified to use omap shared clock framework by
   9  *  Tony Lindgren <tony@atomide.com>
  10  *
  11  *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
  12  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/device.h>
  21 #include <linux/list.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <linux/io.h>
  27
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/sram.h>
  30 #include <asm/div64.h>
  31
  32 #include "memory.h"
  33 #include "clock.h"
  34 #include "clock24xx.h"
  35 #include "prm.h"
  36 #include "prm_regbits_24xx.h"
  37 #include "cm.h"
  38 #include "cm_regbits_24xx.h"
  39
  40 #undef DEBUG
  41
  42 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
  43 #define EN_APLL_STOPPED                 0
  44 #define EN_APLL_LOCKED                  3
  45
  46 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
  47 #define APLLS_CLKIN_19_2MHZ             0
  48 #define APLLS_CLKIN_13MHZ               2
  49 #define APLLS_CLKIN_12MHZ               3
  50
  51 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
  52
  53 static struct prcm_config *curr_prcm_set;
  54 static struct clk *vclk;
  55 static struct clk *sclk;
  56
  57 /*-------------------------------------------------------------------------
  58  * Omap24xx specific clock functions
  59  *-------------------------------------------------------------------------*/
  60
  61 /* This actually returns the rate of core_ck, not dpll_ck. */
  62 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
  63 {
  64         long long dpll_clk;
  65         u8 amult;
  66
  67         dpll_clk = omap2_get_dpll_rate(tclk);
  68
  69         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
  70         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
  71         dpll_clk *= amult;
  72
  73         return dpll_clk;
  74 }
  75
  76 static int omap2_enable_osc_ck(struct clk *clk)
  77 {
  78         u32 pcc;
  79
  80         pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
  81
  82         prm_write_reg(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
  83                       OMAP24XX_PRCM_CLKSRC_CTRL);
  84
  85         return 0;
  86 }
  87
  88 static void omap2_disable_osc_ck(struct clk *clk)
  89 {
  90         u32 pcc;
  91
  92         pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
  93
  94         prm_write_reg(pcc | OMAP_AUTOEXTCLKMODE_MASK,
  95                       OMAP24XX_PRCM_CLKSRC_CTRL);
  96 }
  97
  98 /* Enable an APLL if off */
  99 static int omap2_clk_fixed_enable(struct clk *clk)
 100 {
 101         u32 cval, apll_mask;
 102
 103         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 104
 105         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 106
 107         if ((cval & apll_mask) == apll_mask)
 108                 return 0;   /* apll already enabled */
 109
 110         cval &= ~apll_mask;
 111         cval |= apll_mask;
 112         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 113
 114         if (clk == &apll96_ck)
 115                 cval = OMAP24XX_ST_96M_APLL;
 116         else if (clk == &apll54_ck)
 117                 cval = OMAP24XX_ST_54M_CLK;
 118
 119         omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
 120                             clk->name);
 121
 122         /*
 123          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
 124          * fails?
 125          */
 126         return 0;
 127 }
 128
 129 /* Stop APLL */
 130 static void omap2_clk_fixed_disable(struct clk *clk)
 131 {
 132         u32 cval;
 133
 134         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 135         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
 136         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 137 }
 138
 139 /*
 140  * Uses the current prcm set to tell if a rate is valid.
 141  * You can go slower, but not faster within a given rate set.
 142  */
 143 static u32 omap2_dpll_round_rate(unsigned long target_rate)
 144 {
 145         u32 high, low, core_clk_src;
 146
 147         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 148         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 149
 150         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
 151                 high = curr_prcm_set->dpll_speed * 2;
 152                 low = curr_prcm_set->dpll_speed;
 153         } else {                                /* DPLL clockout x 2 */
 154                 high = curr_prcm_set->dpll_speed;
 155                 low = curr_prcm_set->dpll_speed / 2;
 156         }
 157
 158 #ifdef DOWN_VARIABLE_DPLL
 159         if (target_rate > high)
 160                 return high;
 161         else
 162                 return target_rate;
 163 #else
 164         if (target_rate > low)
 165                 return high;
 166         else
 167                 return low;
 168 #endif
 169
 170 }
 171
 172 static void omap2_dpll_recalc(struct clk *clk)
 173 {
 174         clk->rate = omap2_get_dpll_rate_24xx(clk);
 175
 176         propagate_rate(clk);
 177 }
 178
 179 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
 180 {
 181         u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
 182         u32 bypass = 0;
 183         struct prcm_config tmpset;
 184         const struct dpll_data *dd;
 185         int ret = -EINVAL;
 186
 187         local_irq_save(flags);
 188         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 189         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 190         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 191
 192         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 193                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 194         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 195                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 196         } else if (rate != cur_rate) {
 197                 valid_rate = omap2_dpll_round_rate(rate);
 198                 if (valid_rate != rate)
 199                         goto dpll_exit;
 200
 201                 if (mult == 1)
 202                         low = curr_prcm_set->dpll_speed;
 203                 else
 204                         low = curr_prcm_set->dpll_speed / 2;
 205
 206                 dd = clk->dpll_data;
 207                 if (!dd)
 208                         goto dpll_exit;
 209
 210                 tmpset.cm_clksel1_pll = cm_read_reg(dd->mult_div1_reg);
 211                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
 212                                            dd->div1_mask);
 213                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 214                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 215                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 216                 if (rate > low) {
 217                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
 218                         mult = ((rate / 2) / 1000000);
 219                         done_rate = CORE_CLK_SRC_DPLL_X2;
 220                 } else {
 221                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
 222                         mult = (rate / 1000000);
 223                         done_rate = CORE_CLK_SRC_DPLL;
 224                 }
 225                 tmpset.cm_clksel1_pll |= (div << mask_to_shift(dd->mult_mask));
 226                 tmpset.cm_clksel1_pll |= (mult << mask_to_shift(dd->div1_mask));
 227
 228                 /* Worst case */
 229                 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
 230
 231                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 232                         bypass = 1;
 233
 234                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
 235
 236                 /* Force dll lock mode */
 237                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 238                                bypass);
 239
 240                 /* Errata: ret dll entry state */
 241                 omap2_init_memory_params(omap2_dll_force_needed());
 242                 omap2_reprogram_sdrc(done_rate, 0);
 243         }
 244         omap2_dpll_recalc(&dpll_ck);
 245         ret = 0;
 246
 247 dpll_exit:
 248         local_irq_restore(flags);
 249         return(ret);
 250 }
 251
 252 /**
 253  * omap2_table_mpu_recalc - just return the MPU speed
 254  * @clk: virt_prcm_set struct clk
 255  *
 256  * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 257  */
 258 static void omap2_table_mpu_recalc(struct clk *clk)
 259 {
 260         clk->rate = curr_prcm_set->mpu_speed;
 261 }
 262
 263 /*
 264  * Look for a rate equal or less than the target rate given a configuration set.
 265  *
 266  * What's not entirely clear is "which" field represents the key field.
 267  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 268  * just uses the ARM rates.
 269  */
 270 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 271 {
 272         struct prcm_config *ptr;
 273         long highest_rate;
 274
 275         if (clk != &virt_prcm_set)
 276                 return -EINVAL;
 277
 278         highest_rate = -EINVAL;
 279
 280         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 281                 if (!(ptr->flags & cpu_mask))
 282                         continue;
 283                 if (ptr->xtal_speed != sys_ck.rate)
 284                         continue;
 285
 286                 highest_rate = ptr->mpu_speed;
 287
 288                 /* Can check only after xtal frequency check */
 289                 if (ptr->mpu_speed <= rate)
 290                         break;
 291         }
 292         return highest_rate;
 293 }
 294
 295 /* Sets basic clocks based on the specified rate */
 296 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 297 {
 298         u32 flags, cur_rate, done_rate, bypass = 0, tmp;
 299         struct prcm_config *prcm;
 300         unsigned long found_speed = 0;
 301
 302         if (clk != &virt_prcm_set)
 303                 return -EINVAL;
 304
 305         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 306                 if (!(prcm->flags & cpu_mask))
 307                         continue;
 308
 309                 if (prcm->xtal_speed != sys_ck.rate)
 310                         continue;
 311
 312                 if (prcm->mpu_speed <= rate) {
 313                         found_speed = prcm->mpu_speed;
 314                         break;
 315                 }
 316         }
 317
 318         if (!found_speed) {
 319                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 320                        rate / 1000000);
 321                 return -EINVAL;
 322         }
 323
 324         curr_prcm_set = prcm;
 325         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 326
 327         if (prcm->dpll_speed == cur_rate / 2) {
 328                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 329         } else if (prcm->dpll_speed == cur_rate * 2) {
 330                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 331         } else if (prcm->dpll_speed != cur_rate) {
 332                 local_irq_save(flags);
 333
 334                 if (prcm->dpll_speed == prcm->xtal_speed)
 335                         bypass = 1;
 336
 337                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
 338                     CORE_CLK_SRC_DPLL_X2)
 339                         done_rate = CORE_CLK_SRC_DPLL_X2;
 340                 else
 341                         done_rate = CORE_CLK_SRC_DPLL;
 342
 343                 /* MPU divider */
 344                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 345
 346                 /* dsp + iva1 div(2420), iva2.1(2430) */
 347                 cm_write_mod_reg(prcm->cm_clksel_dsp,
 348                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
 349
 350                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 351
 352                 /* Major subsystem dividers */
 353                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
 354                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
 355                 if (cpu_is_omap2430())
 356                         cm_write_mod_reg(prcm->cm_clksel_mdm,
 357                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 358
 359                 /* x2 to enter init_mem */
 360                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 361
 362                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
 363                                bypass);
 364
 365                 omap2_init_memory_params(omap2_dll_force_needed());
 366                 omap2_reprogram_sdrc(done_rate, 0);
 367
 368                 local_irq_restore(flags);
 369         }
 370         omap2_dpll_recalc(&dpll_ck);
 371
 372         return 0;
 373 }
 374
 375 static struct clk_functions omap2_clk_functions = {
 376         .clk_enable             = omap2_clk_enable,
 377         .clk_disable            = omap2_clk_disable,
 378         .clk_round_rate         = omap2_clk_round_rate,
 379         .clk_set_rate           = omap2_clk_set_rate,
 380         .clk_set_parent         = omap2_clk_set_parent,
 381         .clk_disable_unused     = omap2_clk_disable_unused,
 382 };
 383
 384 static u32 omap2_get_apll_clkin(void)
 385 {
 386         u32 aplls, sclk = 0;
 387
 388         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 389         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
 390         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 391
 392         if (aplls == APLLS_CLKIN_19_2MHZ)
 393                 sclk = 19200000;
 394         else if (aplls == APLLS_CLKIN_13MHZ)
 395                 sclk = 13000000;
 396         else if (aplls == APLLS_CLKIN_12MHZ)
 397                 sclk = 12000000;
 398
 399         return sclk;
 400 }
 401
 402 static u32 omap2_get_sysclkdiv(void)
 403 {
 404         u32 div;
 405
 406         div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
 407         div &= OMAP_SYSCLKDIV_MASK;
 408         div >>= OMAP_SYSCLKDIV_SHIFT;
 409
 410         return div;
 411 }
 412
 413 static void omap2_osc_clk_recalc(struct clk *clk)
 414 {
 415         clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
 416         propagate_rate(clk);
 417 }
 418
 419 static void omap2_sys_clk_recalc(struct clk *clk)
 420 {
 421         clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
 422         propagate_rate(clk);
 423 }
 424
 425 /*
 426  * Set clocks for bypass mode for reboot to work.
 427  */
 428 void omap2_clk_prepare_for_reboot(void)
 429 {
 430         u32 rate;
 431
 432         if (vclk == NULL || sclk == NULL)
 433                 return;
 434
 435         rate = clk_get_rate(sclk);
 436         clk_set_rate(vclk, rate);
 437 }
 438
 439 /*
 440  * Switch the MPU rate if specified on cmdline.
 441  * We cannot do this early until cmdline is parsed.
 442  */
 443 static int __init omap2_clk_arch_init(void)
 444 {
 445         if (!mpurate)
 446                 return -EINVAL;
 447
 448         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
 449                 printk(KERN_ERR "Could not find matching MPU rate\n");
 450
 451         recalculate_root_clocks();
 452
 453         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
 454                "%ld.%01ld/%ld/%ld MHz\n",
 455                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 456                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 457
 458         return 0;
 459 }
 460 arch_initcall(omap2_clk_arch_init);
 461
 462 int __init omap2_clk_init(void)
 463 {
 464         struct prcm_config *prcm;
 465         struct clk **clkp;
 466         u32 clkrate;
 467
 468         if (cpu_is_omap242x())
 469                 cpu_mask = RATE_IN_242X;
 470         else if (cpu_is_omap2430())
 471                 cpu_mask = RATE_IN_243X;
 472
 473         clk_init(&omap2_clk_functions);
 474
 475         omap2_osc_clk_recalc(&osc_ck);
 476
 477         for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
 478              clkp++) {
 479
 480                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
 481                         clk_register(*clkp);
 482                         continue;
 483                 }
 484
 485                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && (cpu_is_omap2430() || cpu_is_omap34xx())) {
 486                         clk_register(*clkp);
 487                         continue;
 488                 }
 489         }
 490
 491         /* Check the MPU rate set by bootloader */
 492         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
 493         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 494                 if (!(prcm->flags & cpu_mask))
 495                         continue;
 496                 if (prcm->xtal_speed != sys_ck.rate)
 497                         continue;
 498                 if (prcm->dpll_speed <= clkrate)
 499                          break;
 500         }
 501         curr_prcm_set = prcm;
 502
 503         recalculate_root_clocks();
 504
 505         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
 506                "%ld.%01ld/%ld/%ld MHz\n",
 507                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 508                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 509
 510         /*
 511          * Only enable those clocks we will need, let the drivers
 512          * enable other clocks as necessary
 513          */
 514         clk_enable_init_clocks();
 515
 516         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
 517         vclk = clk_get(NULL, "virt_prcm_set");
 518         sclk = clk_get(NULL, "sys_ck");
 519
 520         return 0;
 521 }