2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
30 #include <mach/clock.h>
31 #include <mach/sram.h>
32 #include <asm/div64.h>
34 #include <mach/sdrc.h>
36 #include "clock34xx.h"
38 #include "prm-regbits-34xx.h"
40 #include "cm-regbits-34xx.h"
42 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
43 #define DPLL_AUTOIDLE_DISABLE 0x0
44 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
46 #define MAX_DPLL_WAIT_TRIES 1000000
49 * omap3_dpll_recalc - recalculate DPLL rate
50 * @clk: DPLL struct clk
52 * Recalculate and propagate the DPLL rate.
54 static void omap3_dpll_recalc(struct clk *clk)
56 clk->rate = omap2_get_dpll_rate(clk);
61 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
62 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
64 const struct dpll_data *dd;
69 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
70 v &= ~dd->enable_mask;
71 v |= clken_bits << __ffs(dd->enable_mask);
72 cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
75 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
76 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
78 const struct dpll_data *dd;
84 state <<= __ffs(dd->idlest_mask);
86 while (((cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg)
87 & dd->idlest_mask) != state) &&
88 i < MAX_DPLL_WAIT_TRIES) {
93 if (i == MAX_DPLL_WAIT_TRIES) {
94 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
95 clk->name, (state) ? "locked" : "bypassed");
97 pr_debug("clock: %s transition to '%s' in %d loops\n",
98 clk->name, (state) ? "locked" : "bypassed", i);
106 /* From 3430 TRM ES2 4.7.6.2 */
107 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
112 fint = clk->parent->rate / (n + 1);
114 pr_debug("clock: fint is %lu\n", fint);
116 if (fint >= 750000 && fint <= 1000000)
118 else if (fint > 1000000 && fint <= 1250000)
120 else if (fint > 1250000 && fint <= 1500000)
122 else if (fint > 1500000 && fint <= 1750000)
124 else if (fint > 1750000 && fint <= 2100000)
126 else if (fint > 7500000 && fint <= 10000000)
128 else if (fint > 10000000 && fint <= 12500000)
130 else if (fint > 12500000 && fint <= 15000000)
132 else if (fint > 15000000 && fint <= 17500000)
134 else if (fint > 17500000 && fint <= 21000000)
137 pr_debug("clock: unknown freqsel setting for %d\n", n);
142 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
145 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
146 * @clk: pointer to a DPLL struct clk
148 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
149 * readiness before returning. Will save and restore the DPLL's
150 * autoidle state across the enable, per the CDP code. If the DPLL
151 * locked successfully, return 0; if the DPLL did not lock in the time
152 * allotted, or DPLL3 was passed in, return -EINVAL.
154 static int _omap3_noncore_dpll_lock(struct clk *clk)
159 if (clk == &dpll3_ck)
162 pr_debug("clock: locking DPLL %s\n", clk->name);
164 ai = omap3_dpll_autoidle_read(clk);
166 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
170 * If no downstream clocks are enabled, CM_IDLEST bit
171 * may never become active, so don't wait for DPLL to lock.
174 omap3_dpll_allow_idle(clk);
176 r = _omap3_wait_dpll_status(clk, 1);
177 omap3_dpll_deny_idle(clk);
184 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
185 * @clk: pointer to a DPLL struct clk
187 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
188 * bypass mode, the DPLL's rate is set equal to its parent clock's
189 * rate. Waits for the DPLL to report readiness before returning.
190 * Will save and restore the DPLL's autoidle state across the enable,
191 * per the CDP code. If the DPLL entered bypass mode successfully,
192 * return 0; if the DPLL did not enter bypass in the time allotted, or
193 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
196 static int _omap3_noncore_dpll_bypass(struct clk *clk)
201 if (clk == &dpll3_ck)
204 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
207 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
210 ai = omap3_dpll_autoidle_read(clk);
212 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
214 r = _omap3_wait_dpll_status(clk, 0);
217 omap3_dpll_allow_idle(clk);
219 omap3_dpll_deny_idle(clk);
225 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
226 * @clk: pointer to a DPLL struct clk
228 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
229 * restore the DPLL's autoidle state across the stop, per the CDP
230 * code. If DPLL3 was passed in, or the DPLL does not support
231 * low-power stop, return -EINVAL; otherwise, return 0.
233 static int _omap3_noncore_dpll_stop(struct clk *clk)
237 if (clk == &dpll3_ck)
240 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
243 pr_debug("clock: stopping DPLL %s\n", clk->name);
245 ai = omap3_dpll_autoidle_read(clk);
247 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
250 omap3_dpll_allow_idle(clk);
252 omap3_dpll_deny_idle(clk);
258 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
259 * @clk: pointer to a DPLL struct clk
261 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
262 * The choice of modes depends on the DPLL's programmed rate: if it is
263 * the same as the DPLL's parent clock, it will enter bypass;
264 * otherwise, it will enter lock. This code will wait for the DPLL to
265 * indicate readiness before returning, unless the DPLL takes too long
266 * to enter the target state. Intended to be used as the struct clk's
267 * enable function. If DPLL3 was passed in, or the DPLL does not
268 * support low-power stop, or if the DPLL took too long to enter
269 * bypass or lock, return -EINVAL; otherwise, return 0.
271 static int omap3_noncore_dpll_enable(struct clk *clk)
274 struct dpll_data *dd;
276 if (clk == &dpll3_ck)
283 if (clk->rate == dd->bypass_clk->rate)
284 r = _omap3_noncore_dpll_bypass(clk);
286 r = _omap3_noncore_dpll_lock(clk);
289 clk->rate = omap2_get_dpll_rate(clk);
295 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
296 * @clk: pointer to a DPLL struct clk
298 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
299 * The choice of modes depends on the DPLL's programmed rate: if it is
300 * the same as the DPLL's parent clock, it will enter bypass;
301 * otherwise, it will enter lock. This code will wait for the DPLL to
302 * indicate readiness before returning, unless the DPLL takes too long
303 * to enter the target state. Intended to be used as the struct clk's
304 * enable function. If DPLL3 was passed in, or the DPLL does not
305 * support low-power stop, or if the DPLL took too long to enter
306 * bypass or lock, return -EINVAL; otherwise, return 0.
308 static void omap3_noncore_dpll_disable(struct clk *clk)
310 if (clk == &dpll3_ck)
313 _omap3_noncore_dpll_stop(clk);
317 /* Non-CORE DPLL rate set code */
320 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
321 * @clk: struct clk * of DPLL to set
322 * @m: DPLL multiplier to set
323 * @n: DPLL divider to set
324 * @freqsel: FREQSEL value to set
326 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
327 * lock.. Returns -EINVAL upon error, or 0 upon success.
329 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
331 struct dpll_data *dd;
342 * According to the 12-5 CDP code from TI, "Limitation 2.5"
343 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
346 if (omap_rev() == OMAP3430_REV_ES1_0 &&
347 !strcmp("dpll4_ck", clk->name)) {
348 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
349 "silicon 'Limitation 2.5' on 3430ES1.\n");
353 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
354 _omap3_noncore_dpll_bypass(clk);
356 /* Set jitter correction */
357 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
358 v &= ~dd->freqsel_mask;
359 v |= freqsel << __ffs(dd->freqsel_mask);
360 cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
362 /* Set DPLL multiplier, divider */
363 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
364 v &= ~(dd->mult_mask | dd->div1_mask);
365 v |= m << __ffs(dd->mult_mask);
366 v |= (n - 1) << __ffs(dd->div1_mask);
367 cm_write_mod_reg(v, clk->prcm_mod, dd->mult_div1_reg);
369 /* We let the clock framework set the other output dividers later */
371 /* REVISIT: Set ramp-up delay? */
373 _omap3_noncore_dpll_lock(clk);
379 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
380 * @clk: struct clk * of DPLL to set
381 * @rate: rounded target rate
383 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
384 * low-power bypass, and the target rate is the bypass source clock
385 * rate, then configure the DPLL for bypass. Otherwise, round the
386 * target rate if it hasn't been done already, then program and lock
387 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
389 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
392 struct dpll_data *dd;
402 if (rate == omap2_get_dpll_rate(clk))
405 if (dd->bypass_clk->rate == rate &&
406 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
408 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
410 ret = _omap3_noncore_dpll_bypass(clk);
416 if (dd->last_rounded_rate != rate)
417 omap2_dpll_round_rate(clk, rate);
419 if (dd->last_rounded_rate == 0)
422 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
426 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
429 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
430 dd->last_rounded_n, freqsel);
437 omap3_dpll_recalc(clk);
444 * CORE DPLL (DPLL3) rate programming functions
446 * These call into SRAM code to do the actual CM writes, since the SDRAM
447 * is clocked from DPLL3.
451 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
452 * @clk: struct clk * of DPLL to set
453 * @rate: rounded target rate
455 * Program the DPLL M2 divider with the rounded target rate. Returns
456 * -EINVAL upon error, or 0 upon success.
458 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
461 unsigned long validrate, sdrcrate;
462 struct omap_sdrc_params *sp;
467 if (clk != &dpll3_m2_ck)
470 if (rate == clk->rate)
473 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
474 if (validrate != rate)
477 sdrcrate = sdrc_ick.rate;
478 if (rate > clk->rate)
479 sdrcrate <<= ((rate / clk->rate) - 1);
481 sdrcrate >>= ((clk->rate / rate) - 1);
483 sp = omap2_sdrc_get_params(sdrcrate);
487 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
489 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
490 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
492 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
493 WARN_ON(new_div != 1 && new_div != 2);
495 /* REVISIT: Add SDRC_MR changing to this code also */
497 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
498 sp->actim_ctrlb, new_div);
501 omap2_clksel_recalc(clk);
507 /* DPLL autoidle read/set code */
511 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
512 * @clk: struct clk * of the DPLL to read
514 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
515 * -EINVAL if passed a null pointer or if the struct clk does not
516 * appear to refer to a DPLL.
518 static u32 omap3_dpll_autoidle_read(struct clk *clk)
520 const struct dpll_data *dd;
523 if (!clk || !clk->dpll_data)
528 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
529 v &= dd->autoidle_mask;
530 v >>= __ffs(dd->autoidle_mask);
536 * omap3_dpll_allow_idle - enable DPLL autoidle bits
537 * @clk: struct clk * of the DPLL to operate on
539 * Enable DPLL automatic idle control. This automatic idle mode
540 * switching takes effect only when the DPLL is locked, at least on
541 * OMAP3430. The DPLL will enter low-power stop when its downstream
542 * clocks are gated. No return value.
544 static void omap3_dpll_allow_idle(struct clk *clk)
546 const struct dpll_data *dd;
549 if (!clk || !clk->dpll_data)
555 * REVISIT: CORE DPLL can optionally enter low-power bypass
556 * by writing 0x5 instead of 0x1. Add some mechanism to
557 * optionally enter this mode.
559 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
560 v &= ~dd->autoidle_mask;
561 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
562 cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
566 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
567 * @clk: struct clk * of the DPLL to operate on
569 * Disable DPLL automatic idle control. No return value.
571 static void omap3_dpll_deny_idle(struct clk *clk)
573 const struct dpll_data *dd;
576 if (!clk || !clk->dpll_data)
581 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
582 v &= ~dd->autoidle_mask;
583 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
584 cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
587 /* Clock control for DPLL outputs */
590 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
591 * @clk: DPLL output struct clk
593 * Using parent clock DPLL data, look up DPLL state. If locked, set our
594 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
596 static void omap3_clkoutx2_recalc(struct clk *clk)
598 const struct dpll_data *dd;
602 /* Walk up the parents of clk, looking for a DPLL */
604 while (pclk && !pclk->dpll_data)
607 /* clk does not have a DPLL as a parent? */
610 dd = pclk->dpll_data;
612 WARN_ON(!dd->idlest_reg || !dd->idlest_mask);
614 v = cm_read_mod_reg(pclk->prcm_mod, dd->idlest_reg) & dd->idlest_mask;
616 clk->rate = clk->parent->rate;
618 clk->rate = clk->parent->rate * 2;
620 if (clk->flags & RATE_PROPAGATES)
624 /* Common clock code */
627 * As it is structured now, this will prevent an OMAP2/3 multiboot
628 * kernel from compiling. This will need further attention.
630 #if defined(CONFIG_ARCH_OMAP3)
632 static struct clk_functions omap2_clk_functions = {
633 .clk_enable = omap2_clk_enable,
634 .clk_disable = omap2_clk_disable,
635 .clk_round_rate = omap2_clk_round_rate,
636 .clk_set_rate = omap2_clk_set_rate,
637 .clk_set_parent = omap2_clk_set_parent,
638 .clk_disable_unused = omap2_clk_disable_unused,
642 * Set clocks for bypass mode for reboot to work.
644 void omap2_clk_prepare_for_reboot(void)
646 /* REVISIT: Not ready for 343x */
650 if (vclk == NULL || sclk == NULL)
653 rate = clk_get_rate(sclk);
654 clk_set_rate(vclk, rate);
658 /* REVISIT: Move this init stuff out into clock.c */
661 * Switch the MPU rate if specified on cmdline.
662 * We cannot do this early until cmdline is parsed.
664 static int __init omap2_clk_arch_init(void)
669 /* REVISIT: not yet ready for 343x */
671 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
672 printk(KERN_ERR "Could not find matching MPU rate\n");
675 recalculate_root_clocks();
677 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
678 "%ld.%01ld/%ld/%ld MHz\n",
679 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
680 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
684 arch_initcall(omap2_clk_arch_init);
686 int __init omap2_clk_init(void)
688 /* struct prcm_config *prcm; */
693 /* REVISIT: Ultimately this will be used for multiboot */
695 if (cpu_is_omap242x()) {
696 cpu_mask = RATE_IN_242X;
697 cpu_clkflg = CLOCK_IN_OMAP242X;
698 clkp = onchip_24xx_clks;
699 } else if (cpu_is_omap2430()) {
700 cpu_mask = RATE_IN_243X;
701 cpu_clkflg = CLOCK_IN_OMAP243X;
702 clkp = onchip_24xx_clks;
705 if (cpu_is_omap34xx()) {
706 cpu_mask = RATE_IN_343X;
707 cpu_clkflg = CLOCK_IN_OMAP343X;
708 clkp = onchip_34xx_clks;
711 * Update this if there are further clock changes between ES2
712 * and production parts
714 if (omap_rev() == OMAP3430_REV_ES1_0) {
715 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
716 cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
718 cpu_mask |= RATE_IN_3430ES2;
719 cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
723 clk_init(&omap2_clk_functions);
725 for (clkp = onchip_34xx_clks;
726 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
728 if ((*clkp)->flags & cpu_clkflg) {
730 omap2_init_clk_clkdm(*clkp);
734 /* REVISIT: Not yet ready for OMAP3 */
736 /* Check the MPU rate set by bootloader */
737 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
738 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
739 if (!(prcm->flags & cpu_mask))
741 if (prcm->xtal_speed != sys_ck.rate)
743 if (prcm->dpll_speed <= clkrate)
746 curr_prcm_set = prcm;
749 recalculate_root_clocks();
751 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
752 "%ld.%01ld/%ld/%ld MHz\n",
753 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
754 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
757 * Only enable those clocks we will need, let the drivers
758 * enable other clocks as necessary
760 clk_enable_init_clocks();
762 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
763 /* REVISIT: not yet ready for 343x */
765 vclk = clk_get(NULL, "virt_prcm_set");
766 sclk = clk_get(NULL, "sys_ck");