arch/arm/mach-omap2/cm.h

   1 #ifndef __ARCH_ASM_MACH_OMAP2_CM_H
   2 #define __ARCH_ASM_MACH_OMAP2_CM_H
   3
   4 /*
   5  * OMAP2/3 Clock Management (CM) register definitions
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <asm/io.h>
  18
  19 #include "prcm-common.h"
  20
  21 #ifndef __ASSEMBLER__
  22 #define OMAP_CM_REGADDR(module, reg)                                    \
  23         (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
  24 #else
  25 #define OMAP2420_CM_REGADDR(module, reg)                                \
  26                         IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
  27 #define OMAP2430_CM_REGADDR(module, reg)                                \
  28                         IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
  29 #define OMAP34XX_CM_REGADDR(module, reg)                                \
  30                         IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
  31 #endif
  32
  33 /*
  34  * Architecture-specific global CM registers
  35  * Use cm_{read,write}_reg() with these registers.
  36  * These registers appear once per CM module.
  37  */
  38
  39 #define OMAP3430_CM_REVISION            OMAP_CM_REGADDR(OCP_MOD, 0x0000)
  40 #define OMAP3430_CM_SYSCONFIG           OMAP_CM_REGADDR(OCP_MOD, 0x0010)
  41 #define OMAP3430_CM_POLCTRL             OMAP_CM_REGADDR(OCP_MOD, 0x009c)
  42
  43 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
  44
  45 #ifndef __ASSEMBLER__
  46 /* Clock management global register get/set */
  47
  48 static void __attribute__((unused)) cm_write_reg(u32 val, void __iomem *addr)
  49 {
  50         pr_debug("cm_write_reg: writing 0x%0x to 0x%0x\n", val, (u32)addr);
  51
  52         __raw_writel(val, addr);
  53 }
  54
  55 static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr)
  56 {
  57         return __raw_readl(addr);
  58 }
  59
  60 /* Read-modify-write bits in a CM register */
  61 static u32 __attribute__((unused)) cm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *va)
  62 {
  63         u32 v;
  64
  65         v = cm_read_reg(va);
  66         v &= ~mask;
  67         v |= bits;
  68         cm_write_reg(v, va);
  69
  70         return v;
  71 }
  72
  73 #endif
  74
  75 /*
  76  * Module specific CM registers from CM_BASE + domain offset
  77  * Use cm_{read,write}_mod_reg() with these registers.
  78  * These register offsets generally appear in more than one PRCM submodule.
  79  */
  80
  81 /* Common between 24xx and 34xx */
  82
  83 #define CM_FCLKEN                                       0x0000
  84 #define CM_FCLKEN1                                      CM_FCLKEN
  85 #define CM_CLKEN                                        CM_FCLKEN
  86 #define CM_ICLKEN                                       0x0010
  87 #define CM_ICLKEN1                                      CM_ICLKEN
  88 #define CM_ICLKEN2                                      0x0014
  89 #define CM_ICLKEN3                                      0x0018
  90 #define CM_IDLEST                                       0x0020
  91 #define CM_IDLEST1                                      CM_IDLEST
  92 #define CM_IDLEST2                                      0x0024
  93 #define CM_AUTOIDLE                                     0x0030
  94 #define CM_AUTOIDLE1                                    CM_AUTOIDLE
  95 #define CM_AUTOIDLE2                                    0x0034
  96 #define CM_AUTOIDLE3                                    0x0038
  97 #define CM_CLKSEL                                       0x0040
  98 #define CM_CLKSEL1                                      CM_CLKSEL
  99 #define CM_CLKSEL2                                      0x0044
 100 #define CM_CLKSTCTRL                                    0x0048
 101
 102 /* Architecture-specific registers */
 103
 104 #define OMAP24XX_CM_FCLKEN2                             0x0004
 105 #define OMAP24XX_CM_ICLKEN4                             0x001c
 106 #define OMAP24XX_CM_AUTOIDLE4                           0x003c
 107
 108 #define OMAP2430_CM_IDLEST3                             0x0028
 109
 110 #define OMAP3430_CM_CLKEN_PLL                           0x0004
 111 #define OMAP3430ES2_CM_CLKEN2                           0x0004
 112 #define OMAP3430ES2_CM_FCLKEN3                          0x0008
 113 #define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
 114 #define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
 115 #define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
 116 #define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
 117 #define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
 118 #define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
 119 #define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
 120 #define OMAP3430_CM_CLKSEL3                             CM_CLKSTCTRL
 121 #define OMAP3430_CM_CLKSTST                             0x004c
 122 #define OMAP3430ES2_CM_CLKSEL4                          0x004c
 123 #define OMAP3430ES2_CM_CLKSEL5                          0x0050
 124 #define OMAP3430_CM_CLKSEL2_EMU                         0x0050
 125 #define OMAP3430_CM_CLKSEL3_EMU                         0x0054
 126
 127
 128 /* Clock management domain register get/set */
 129
 130 #ifndef __ASSEMBLER__
 131 static void __attribute__((unused)) cm_write_mod_reg(u32 val, s16 module,
 132                                                         s16 idx)
 133 {
 134         cm_write_reg(val, OMAP_CM_REGADDR(module, idx));
 135 }
 136
 137 static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx)
 138 {
 139         return cm_read_reg(OMAP_CM_REGADDR(module, idx));
 140 }
 141
 142 /* Read-modify-write bits in a CM register (by domain) */
 143 static inline u32 __attribute__((unused)) cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 144 {
 145         return cm_rmw_reg_bits(mask, bits, OMAP_CM_REGADDR(module, idx));
 146 }
 147
 148 static inline u32 __attribute__((unused)) cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 149 {
 150         return cm_rmw_mod_reg_bits(bits, bits, module, idx);
 151 }
 152
 153 static inline u32 __attribute__((unused)) cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 154 {
 155         return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 156 }
 157
 158 #endif
 159
 160 /* CM register bits shared between 24XX and 3430 */
 161
 162 /* CM_CLKSEL_GFX */
 163 #define OMAP_CLKSEL_GFX_SHIFT                           0
 164 #define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
 165
 166 /* CM_ICLKEN_GFX */
 167 #define OMAP_EN_GFX_SHIFT                               0
 168 #define OMAP_EN_GFX                                     (1 << 0)
 169
 170 /* CM_IDLEST_GFX */
 171 #define OMAP_ST_GFX                                     (1 << 0)
 172
 173
 174 #endif