1 #ifndef __ARCH_ASM_MACH_OMAP2_CM_H
2 #define __ARCH_ASM_MACH_OMAP2_CM_H
5 * OMAP2/3 Clock Management (CM) register definitions
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
19 #include "prcm_common.h"
22 #define OMAP_CM_REGADDR(module, reg) (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + module + reg)
25 * Architecture-specific global CM registers
26 * Use cm_{read,write}_reg() with these registers.
29 #define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000)
30 #define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010)
31 #define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c)
33 #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
36 /* Clock management global register get/set */
38 static void __attribute__((unused)) cm_write_reg(u32 val, void __iomem *addr)
40 pr_debug("cm_write_reg: writing 0x%0x to 0x%0x\n", val, (u32)addr);
42 __raw_writel(val, addr);
45 static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr)
47 return __raw_readl(addr);
52 * Module specific CM registers from CM_BASE + domain offset
53 * Use cm_{read,write}_mod_reg() with these registers.
56 /* Common between 24xx and 34xx */
58 #define CM_FCLKEN1 0x0000
59 #define CM_FCLKEN CM_FCLKEN1
60 #define CM_CLKEN CM_FCLKEN1
61 #define CM_ICLKEN1 0x0010
62 #define CM_ICLKEN CM_ICLKEN1
63 #define CM_ICLKEN2 0x0014
64 #define CM_ICLKEN3 0x0018
65 #define CM_IDLEST1 0x0020
66 #define CM_IDLEST CM_IDLEST1
67 #define CM_IDLEST2 0x0024
68 #define CM_AUTOIDLE 0x0030
69 #define CM_AUTOIDLE1 0x0030
70 #define CM_AUTOIDLE2 0x0034
71 #define CM_CLKSEL 0x0040
72 #define CM_CLKSEL1 CM_CLKSEL
73 #define CM_CLKSEL2 0x0044
74 #define CM_CLKSTCTRL 0x0048
77 /* Architecture-specific registers */
79 #define OMAP24XX_CM_FCLKEN2 0x0004
80 #define OMAP24XX_CM_ICLKEN4 0x001c
81 #define OMAP24XX_CM_AUTOIDLE3 0x0038
82 #define OMAP24XX_CM_AUTOIDLE4 0x003c
84 #define OMAP2430_CM_IDLEST3 0x0028
87 /* Clock management domain register get/set */
89 static void __attribute__((unused)) cm_write_mod_reg(u32 val, s16 module, s16 idx)
91 cm_write_reg(val, OMAP_CM_REGADDR(module, idx));
94 static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx)
96 return cm_read_reg(OMAP_CM_REGADDR(module, idx));
99 /* CM register bits shared between 24XX and 3430 */
102 #define OMAP_CLKSEL_GFX_SHIFT 0
103 #define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
106 #define OMAP_EN_GFX_SHIFT 0
107 #define OMAP_EN_GFX (1 << 0)
110 #define OMAP_ST_GFX (1 << 0)
112 #define OMAP3430_CM_CLKEN_PLL 0x0004
113 #define OMAP3430ES2_CM_CLKEN2 0x0004
114 #define OMAP3430ES2_CM_FCLKEN3 0x0008
115 #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
116 #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
117 #define OMAP3430_CM_CLKSEL1 CM_CLKSEL
118 #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
119 #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
120 #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
121 #define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL
122 #define OMAP3430_CM_CLKSTST 0x004c
123 #define OMAP3430ES2_CM_CLKSEL4 0x004c
124 #define OMAP3430ES2_CM_CLKSEL5 0x0050
125 #define OMAP3430_CM_CLKSEL2_EMU 0x0050
126 #define OMAP3430_CM_CLKSEL3_EMU 0x0054
127 #define OMAP3430_CM_IDLEST3_CORE 0x0028
128 #define OMAP3430_CM_AUTOIDLE3_CORE 0x0038