2 * linux/arch/arm/mach-omap2/pm.c
4 * OMAP2 Power Management Routines
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 * Copyright (C) 2006 Nokia Corporation
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * Amit Kucheria <amit.kucheria@nokia.com>
14 * Igor Stoppa <igor.stoppa@nokia.com>
16 * Based on pm.c for omap1
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/sched.h>
25 #include <linux/proc_fs.h>
27 #include <linux/interrupt.h>
28 #include <linux/sysfs.h>
29 #include <linux/module.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
35 #include <asm/atomic.h>
36 #include <asm/mach/time.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach-types.h>
40 #include <asm/arch/irqs.h>
41 #include <asm/arch/clock.h>
42 #include <asm/arch/sram.h>
43 #include <asm/arch/pm.h>
44 #include <asm/arch/mux.h>
45 #include <asm/arch/dma.h>
46 #include <asm/arch/board.h>
47 #include <asm/arch/gpio.h>
49 #define PRCM_REVISION 0x000
50 #define PRCM_SYSCONFIG 0x010
51 #define PRCM_IRQSTATUS_MPU 0x018
52 #define PRCM_IRQENABLE_MPU 0x01c
53 #define PRCM_VOLTCTRL 0x050
54 #define AUTO_EXTVOLT (1 << 15)
55 #define FORCE_EXTVOLT (1 << 14)
56 #define SETOFF_LEVEL(x) (((x) & 0x3) << 12)
57 #define MEMRETCTRL (1 << 8)
58 #define SETRET_LEVEL(x) (((x) & 0x3) << 6)
59 #define VOLT_LEVEL(x) (((x) & 0x3) << 0)
60 #define PRCM_CLKSRC_CTRL 0x060
61 #define PRCM_CLKOUT_CTRL 0x070
62 #define PRCM_CLKEMUL_CTRL 0x078
63 #define PRCM_CLKCFG_CTRL 0x080
64 #define PRCM_VOLTSETUP 0x090
65 #define PRCM_CLKSSETUP 0x094
68 #define CM_CLKSEL_MPU 0x140
69 #define CM_CLKSTCTRL_MPU 0x148
70 #define AUTOSTAT_MPU (1 << 0)
71 #define PM_WKDEP_MPU 0x1c8
72 #define EN_WKUP (1 << 4)
73 #define EN_GFX (1 << 3)
74 #define EN_DSP (1 << 2)
75 #define EN_MPU (1 << 1)
76 #define EN_CORE (1 << 0)
77 #define PM_PWSTCTRL_MPU 0x1e0
78 #define PM_PWSTST_MPU 0x1e4
81 #define CM_FCLKEN1_CORE 0x200
82 #define CM_FCLKEN2_CORE 0x204
83 #define CM_ICLKEN1_CORE 0x210
84 #define CM_ICLKEN2_CORE 0x214
85 #define CM_ICLKEN4_CORE 0x21c
86 #define CM_IDLEST1_CORE 0x220
87 #define CM_IDLEST2_CORE 0x224
88 #define CM_AUTOIDLE1_CORE 0x230
89 #define CM_AUTOIDLE2_CORE 0x234
90 #define CM_AUTOIDLE3_CORE 0x238
91 #define CM_AUTOIDLE4_CORE 0x23c
92 #define CM_CLKSEL1_CORE 0x240
93 #define CM_CLKSEL2_CORE 0x244
94 #define CM_CLKSTCTRL_CORE 0x248
95 #define AUTOSTAT_DSS (1 << 2)
96 #define AUTOSTAT_L4 (1 << 1)
97 #define AUTOSTAT_L3 (1 << 0)
98 #define PM_WKEN1_CORE 0x2a0
99 #define PM_WKEN2_CORE 0x2a4
100 #define PM_WKST1_CORE 0x2b0
101 #define PM_WKST2_CORE 0x2b4
102 #define PM_WKDEP_CORE 0x2c8
103 #define PM_PWSTCTRL_CORE 0x2e0
104 #define PM_PWSTST_CORE 0x2e4
107 #define CM_CLKSTCTRL_GFX 0x348
108 #define AUTOSTAT_GFX (1 << 0)
109 #define PM_WKDEP_GFX 0x3c8
110 #define PM_PWSTCTRL_GFX 0x3e0
113 #define CM_FCLKEN_WKUP 0x400
114 #define CM_ICLKEN_WKUP 0x410
115 #define CM_AUTOIDLE_WKUP 0x430
116 #define PM_WKEN_WKUP 0x4a0
117 #define EN_GPIOS (1 << 2)
118 #define EN_GPT1 (1 << 0)
119 #define PM_WKST_WKUP 0x4b0
122 #define CM_CLKEN_PLL 0x500
123 #define CM_IDLEST_CKGEN 0x520
124 #define CM_AUTOIDLE_PLL 0x530
125 #define CM_CLKSEL1_PLL 0x540
126 #define CM_CLKSEL2_PLL 0x544
129 #define CM_FCLKEN_DSP 0x800
130 #define CM_ICLKEN_DSP 0x810
131 #define CM_IDLEST_DSP 0x820
132 #define CM_AUTOIDLE_DSP 0x830
133 #define CM_CLKSEL_DSP 0x840
134 #define CM_CLKSTCTRL_DSP 0x848
135 #define AUTOSTAT_IVA (1 << 8)
136 #define AUTOSTAT_DSP (1 << 0)
137 #define RM_RSTCTRL_DSP 0x850
138 #define RM_RSTST_DSP 0x858
139 #define PM_WKDEP_DSP 0x8c8
140 #define PM_PWSTCTRL_DSP 0x8e0
141 #define PM_PWSTST_DSP 0x8e4
143 static void (*omap2_sram_idle)(void);
144 static void (*omap2_sram_suspend)(int dllctrl);
145 static void (*saved_idle)(void);
147 static u32 prcm_base = IO_ADDRESS(OMAP2_PRCM_BASE);
149 static inline void prcm_write_reg(int idx, u32 val)
151 __raw_writel(val, prcm_base + idx);
154 static inline u32 prcm_read_reg(int idx)
156 return __raw_readl(prcm_base + idx);
159 static u32 omap2_read_32k_sync_counter(void)
161 return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
164 #ifdef CONFIG_PM_DEBUG
165 int omap2_pm_debug = 0;
167 static int serial_console_clock_disabled;
168 static int serial_console_uart;
169 static unsigned int serial_console_next_disable;
171 static struct clk *console_iclk, *console_fclk;
173 static void serial_console_kick(void)
175 serial_console_next_disable = omap2_read_32k_sync_counter();
176 /* Keep the clocks on for 4 secs */
177 serial_console_next_disable += 4 * 32768;
180 static void serial_wait_tx(void)
182 static const unsigned long uart_bases[3] = {
183 0x4806a000, 0x4806c000, 0x4806e000
185 unsigned long lsr_reg;
188 /* Wait for TX FIFO and THR to get empty */
189 lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
190 while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
193 serial_console_kick();
196 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
198 switch (serial_console_uart) {
211 static void serial_console_sleep(int enable)
213 if (console_iclk == NULL || console_fclk == NULL)
217 BUG_ON(serial_console_clock_disabled);
218 if (clk_get_usecount(console_fclk) == 0)
220 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
223 clk_disable(console_iclk);
224 clk_disable(console_fclk);
225 serial_console_clock_disabled = 1;
227 int serial_wakeup = 0;
230 switch (serial_console_uart) {
232 l = prcm_read_reg(PM_WKST1_CORE);
237 l = prcm_read_reg(PM_WKST1_CORE);
242 l = prcm_read_reg(PM_WKST2_CORE);
248 serial_console_kick();
249 if (!serial_console_clock_disabled)
251 clk_enable(console_iclk);
252 clk_enable(console_fclk);
253 serial_console_clock_disabled = 0;
257 static void pm_init_serial_console(void)
259 const struct omap_serial_console_config *conf;
263 conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
264 struct omap_serial_console_config);
267 if (conf->console_uart > 3 || conf->console_uart < 1)
269 serial_console_uart = conf->console_uart;
270 sprintf(name, "uart%d_fck", conf->console_uart);
271 console_fclk = clk_get(NULL, name);
272 if (IS_ERR(console_fclk))
275 console_iclk = clk_get(NULL, name);
276 if (IS_ERR(console_fclk))
278 if (console_fclk == NULL || console_iclk == NULL) {
279 serial_console_uart = 0;
282 switch (serial_console_uart) {
284 l = prcm_read_reg(PM_WKEN1_CORE);
286 prcm_write_reg(PM_WKEN1_CORE, l);
289 l = prcm_read_reg(PM_WKEN1_CORE);
291 prcm_write_reg(PM_WKEN1_CORE, l);
294 l = prcm_read_reg(PM_WKEN2_CORE);
296 prcm_write_reg(PM_WKEN2_CORE, l);
301 #define DUMP_REG(reg) \
302 regs[reg_count].name = #reg; \
303 regs[reg_count++].val = prcm_read_reg(reg)
304 #define DUMP_INTC_REG(reg, off) \
305 regs[reg_count].name = #reg; \
306 regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
308 static void omap2_pm_dump(int mode, int resume, unsigned int us)
314 int reg_count = 0, i;
315 const char *s1 = NULL, *s2 = NULL;
320 DUMP_REG(PRCM_IRQENABLE_MPU);
321 DUMP_REG(CM_CLKSTCTRL_MPU);
322 DUMP_REG(PM_PWSTCTRL_MPU);
323 DUMP_REG(PM_PWSTST_MPU);
324 DUMP_REG(PM_WKDEP_MPU);
328 DUMP_INTC_REG(INTC_MIR0, 0x0084);
329 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
330 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
333 DUMP_REG(CM_FCLKEN1_CORE);
334 DUMP_REG(CM_FCLKEN2_CORE);
335 DUMP_REG(CM_FCLKEN_WKUP);
336 DUMP_REG(CM_ICLKEN1_CORE);
337 DUMP_REG(CM_ICLKEN2_CORE);
338 DUMP_REG(CM_ICLKEN_WKUP);
339 DUMP_REG(CM_CLKEN_PLL);
340 DUMP_REG(PRCM_CLKEMUL_CTRL);
341 DUMP_REG(CM_AUTOIDLE_PLL);
342 DUMP_REG(PM_PWSTST_CORE);
343 DUMP_REG(PRCM_CLKSRC_CTRL);
347 DUMP_REG(CM_FCLKEN_DSP);
348 DUMP_REG(CM_ICLKEN_DSP);
349 DUMP_REG(CM_IDLEST_DSP);
350 DUMP_REG(CM_AUTOIDLE_DSP);
351 DUMP_REG(CM_CLKSEL_DSP);
352 DUMP_REG(CM_CLKSTCTRL_DSP);
353 DUMP_REG(RM_RSTCTRL_DSP);
354 DUMP_REG(RM_RSTST_DSP);
355 DUMP_REG(PM_PWSTCTRL_DSP);
356 DUMP_REG(PM_PWSTST_DSP);
359 DUMP_REG(PM_WKST1_CORE);
360 DUMP_REG(PM_WKST2_CORE);
361 DUMP_REG(PM_WKST_WKUP);
362 DUMP_REG(PRCM_IRQSTATUS_MPU);
364 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
365 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
366 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
386 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
387 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
388 jiffies_to_msecs(next_timer_interrupt() - jiffies));
390 printk("--- Going to %s %s\n", s1, s2);
393 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
394 for (i = 0; i < reg_count; i++)
395 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
399 static inline void serial_console_sleep(int enable) {}
400 static inline void pm_init_serial_console(void) {}
401 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
402 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
404 #define omap2_pm_debug 0
408 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
410 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
412 return sprintf(buf, "%hu\n", enable_dyn_sleep);
415 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
419 unsigned short value;
420 if (sscanf(buf, "%hu", &value) != 1 ||
421 (value != 0 && value != 1)) {
422 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
425 enable_dyn_sleep = value;
429 static struct subsys_attribute sleep_while_idle_attr = {
431 .name = __stringify(sleep_while_idle),
434 .show = omap_pm_sleep_while_idle_show,
435 .store = omap_pm_sleep_while_idle_store,
438 static struct clk *osc_ck, *emul_ck;
440 #define CONTROL_DEVCONF __REG32(0x48000274)
441 #define SDRC_DLLA_CTRL __REG32(0x68009060)
443 static int omap2_fclks_active(void)
447 f1 = prcm_read_reg(CM_FCLKEN1_CORE);
448 f2 = prcm_read_reg(CM_FCLKEN2_CORE);
449 serial_console_fclk_mask(&f1, &f2);
455 static int omap2_irq_pending(void)
457 u32 pending_reg = IO_ADDRESS(0x480fe098);
460 for (i = 0; i < 4; i++) {
461 if (__raw_readl(pending_reg))
468 static atomic_t sleep_block = ATOMIC_INIT(0);
470 void omap2_block_sleep(void)
472 atomic_inc(&sleep_block);
475 void omap2_allow_sleep(void)
479 i = atomic_dec_return(&sleep_block);
483 static void omap2_enter_full_retention(void)
487 /* There is 1 reference hold for all children of the oscillator
488 * clock, the following will remove it. If no one else uses the
489 * oscillator itself it will be disabled if/when we enter retention
494 /* Clear old wake-up events */
495 prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
496 prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
497 prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
499 /* Try to enter retention */
500 prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
502 /* Workaround to kill USB */
503 CONTROL_DEVCONF |= 0x00008000;
505 omap2_gpio_prepare_for_retention();
507 if (omap2_pm_debug) {
508 omap2_pm_dump(0, 0, 0);
509 sleep_time = omap2_read_32k_sync_counter();
512 /* One last check for pending IRQs to avoid extra latency due
513 * to sleeping unnecessarily. */
514 if (omap2_irq_pending())
517 serial_console_sleep(1);
518 /* Jump to SRAM suspend code */
519 omap2_sram_suspend(SDRC_DLLA_CTRL);
521 serial_console_sleep(0);
523 if (omap2_pm_debug) {
524 unsigned long long tmp;
527 resume_time = omap2_read_32k_sync_counter();
528 tmp = resume_time - sleep_time;
530 omap2_pm_dump(0, 1, tmp / 32768);
532 omap2_gpio_resume_after_retention();
538 static int omap2_i2c_active(void)
542 l = prcm_read_reg(CM_FCLKEN1_CORE);
543 return l & ((1 << 19) | (1 << 20));
546 static int sti_console_enabled;
548 static int omap2_allow_mpu_retention(void)
552 if (atomic_read(&sleep_block))
555 /* Check for UART2, UART1, McSPI2, McSPI1 and DSS1. */
556 l = prcm_read_reg(CM_FCLKEN1_CORE);
559 /* Check for UART3. */
560 l = prcm_read_reg(CM_FCLKEN2_CORE);
563 if (sti_console_enabled)
569 static void omap2_enter_mpu_retention(void)
574 /* Putting MPU into the WFI state while a transfer is active
575 * seems to cause the I2C block to timeout. Why? Good question. */
576 if (omap2_i2c_active())
579 /* The peripherals seem not to be able to wake up the MPU when
580 * it is in retention mode. */
581 if (omap2_allow_mpu_retention()) {
582 prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
583 prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
584 prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
586 /* Try to enter MPU retention */
587 prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
589 /* Block MPU retention */
590 prcm_write_reg(PM_PWSTCTRL_MPU, 1 << 2);
594 if (omap2_pm_debug) {
595 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
596 sleep_time = omap2_read_32k_sync_counter();
601 if (omap2_pm_debug) {
602 unsigned long long tmp;
605 resume_time = omap2_read_32k_sync_counter();
606 tmp = resume_time - sleep_time;
608 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
612 static int omap2_can_sleep(void)
614 if (!enable_dyn_sleep)
616 if (omap2_fclks_active())
618 if (atomic_read(&sleep_block) > 0)
620 if (clk_get_usecount(osc_ck) > 1)
622 if (omap_dma_running())
628 static void omap2_pm_idle(void)
633 if (!omap2_can_sleep()) {
634 /* timer_dyn_reprogram() takes about 100-200 us to complete.
635 * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
636 * transfer to complete), the increased latency is too much.
638 * omap2_block_sleep() and omap2_allow_sleep() can be used
641 if (atomic_read(&sleep_block) == 0) {
642 timer_dyn_reprogram();
643 if (omap2_irq_pending())
646 omap2_enter_mpu_retention();
651 * Since an interrupt may set up a timer, we don't want to
652 * reprogram the hardware timer with interrupts enabled.
653 * Re-enable interrupts only after returning from idle.
655 timer_dyn_reprogram();
657 if (omap2_irq_pending())
660 omap2_enter_full_retention();
667 static int omap2_pm_prepare(suspend_state_t state)
671 /* We cannot sleep in idle until we have resumed */
672 saved_idle = pm_idle;
676 case PM_SUSPEND_STANDBY:
686 static int omap2_pm_suspend(void)
690 wken_wkup = prcm_read_reg(PM_WKEN_WKUP);
691 prcm_write_reg(PM_WKEN_WKUP, wken_wkup & ~EN_GPT1);
694 mir1 = omap_readl(0x480fe0a4);
695 omap_writel(1 << 5, 0x480fe0ac);
697 omap2_enter_full_retention();
699 omap_writel(mir1, 0x480fe0a4);
700 prcm_write_reg(PM_WKEN_WKUP, wken_wkup);
705 static int omap2_pm_enter(suspend_state_t state)
710 case PM_SUSPEND_STANDBY:
712 ret = omap2_pm_suspend();
721 static int omap2_pm_finish(suspend_state_t state)
723 pm_idle = saved_idle;
727 static struct pm_ops omap_pm_ops = {
728 .prepare = omap2_pm_prepare,
729 .enter = omap2_pm_enter,
730 .finish = omap2_pm_finish,
731 .valid = pm_valid_only_mem,
734 static void __init prcm_setup_regs(void)
738 /* Enable autoidle */
739 prcm_write_reg(PRCM_SYSCONFIG, 1 << 0);
741 /* Set all domain wakeup dependencies */
742 prcm_write_reg(PM_WKDEP_MPU, EN_WKUP);
743 prcm_write_reg(PM_WKDEP_DSP, 0);
744 prcm_write_reg(PM_WKDEP_GFX, 0);
746 l = prcm_read_reg(PM_PWSTCTRL_CORE);
747 /* Enable retention for all memory blocks */
748 l |= (1 << 3) | (1 << 4) | (1 << 5);
749 /* Set power state to RETENTION */
752 prcm_write_reg(PM_PWSTCTRL_CORE, l);
754 prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
756 /* Power down DSP and GFX */
757 prcm_write_reg(PM_PWSTCTRL_DSP, (1 << 18) | 0x03);
758 prcm_write_reg(PM_PWSTCTRL_GFX, (1 << 18) | 0x03);
760 /* Enable clock auto control for all domains */
761 prcm_write_reg(CM_CLKSTCTRL_MPU, AUTOSTAT_MPU);
762 prcm_write_reg(CM_CLKSTCTRL_CORE, AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3);
763 prcm_write_reg(CM_CLKSTCTRL_GFX, AUTOSTAT_GFX);
764 prcm_write_reg(CM_CLKSTCTRL_DSP, AUTOSTAT_IVA | AUTOSTAT_DSP);
766 /* Enable clock autoidle for all domains */
767 prcm_write_reg(CM_AUTOIDLE1_CORE, 0xfffffff9);
768 prcm_write_reg(CM_AUTOIDLE2_CORE, 0x07);
769 prcm_write_reg(CM_AUTOIDLE3_CORE, 0x07);
770 prcm_write_reg(CM_AUTOIDLE4_CORE, 0x1f);
772 prcm_write_reg(CM_AUTOIDLE_DSP, 0x02);
774 /* Put DPLL and both APLLs into autoidle mode */
775 prcm_write_reg(CM_AUTOIDLE_PLL, (0x03 << 0) | (0x03 << 2) | (0x03 << 6));
777 prcm_write_reg(CM_AUTOIDLE_WKUP, 0x3f);
779 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
781 prcm_write_reg(PRCM_CLKSSETUP, 15);
783 /* Configure automatic voltage transition */
784 prcm_write_reg(PRCM_VOLTSETUP, 2);
785 l = AUTO_EXTVOLT | SETOFF_LEVEL(1) | MEMRETCTRL | \
786 SETRET_LEVEL(1) | VOLT_LEVEL(0);
787 prcm_write_reg(PRCM_VOLTCTRL, l);
789 /* Enable wake-up events */
790 prcm_write_reg(PM_WKEN_WKUP, EN_GPIOS | EN_GPT1);
793 int __init omap2_pm_init(void)
797 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
798 l = prcm_read_reg(PRCM_REVISION);
799 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
801 osc_ck = clk_get(NULL, "osc_ck");
802 if (IS_ERR(osc_ck)) {
803 printk(KERN_ERR "could not get osc_ck\n");
807 emul_ck = clk_get(NULL, "emul_ck");
808 if (IS_ERR(emul_ck)) {
809 printk(KERN_ERR "could not get emul_ck\n");
816 pm_init_serial_console();
818 /* Hack to prevent MPU retention when STI console is enabled. */
820 const struct omap_sti_console_config *sti;
822 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
823 struct omap_sti_console_config);
824 if (sti != NULL && sti->enable)
825 sti_console_enabled = 1;
829 * We copy the assembler sleep/wakeup routines to SRAM.
830 * These routines need to be in SRAM as that's the only
831 * memory the MPU can see when it wakes up.
833 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
834 omap24xx_idle_loop_suspend_sz);
835 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
836 omap24xx_cpu_suspend_sz);
838 pm_set_ops(&omap_pm_ops);
839 pm_idle = omap2_pm_idle;
841 l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
843 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
848 late_initcall(omap2_pm_init);