2 * linux/arch/arm/mach-omap2/pm.c
4 * OMAP2 Power Management Routines
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 * Copyright (C) 2006 Nokia Corporation
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * Amit Kucheria <amit.kucheria@nokia.com>
14 * Igor Stoppa <igor.stoppa@nokia.com>
16 * Based on pm.c for omap1
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
23 #include <linux/suspend.h>
24 #include <linux/sched.h>
25 #include <linux/proc_fs.h>
26 #include <linux/interrupt.h>
27 #include <linux/sysfs.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/atomic.h>
35 #include <asm/mach/time.h>
36 #include <asm/mach/irq.h>
37 #include <asm/mach-types.h>
39 #include <asm/arch/irqs.h>
40 #include <asm/arch/clock.h>
41 #include <asm/arch/sram.h>
42 #include <asm/arch/gpio.h>
43 #include <asm/arch/pm.h>
44 #include <asm/arch/mux.h>
45 #include <asm/arch/dma.h>
46 #include <asm/arch/board.h>
47 #include <asm/arch/gpio.h>
50 #include "prm_regbits_24xx.h"
52 #include "cm_regbits_24xx.h"
56 /* These addrs are in assembly language code to be patched at runtime */
57 extern void *omap2_ocs_sdrc_power;
58 extern void *omap2_ocs_sdrc_dlla_ctrl;
60 static void (*omap2_sram_idle)(void);
61 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
62 static void (*saved_idle)(void);
64 static u32 omap2_read_32k_sync_counter(void)
66 return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
69 #ifdef CONFIG_PM_DEBUG
70 int omap2_pm_debug = 0;
72 static int serial_console_clock_disabled;
73 static int serial_console_uart;
74 static unsigned int serial_console_next_disable;
76 static struct clk *console_iclk, *console_fclk;
78 static void serial_console_kick(void)
80 serial_console_next_disable = omap2_read_32k_sync_counter();
81 /* Keep the clocks on for 4 secs */
82 serial_console_next_disable += 4 * 32768;
85 static void serial_wait_tx(void)
87 static const unsigned long uart_bases[3] = {
88 0x4806a000, 0x4806c000, 0x4806e000
90 unsigned long lsr_reg;
93 /* Wait for TX FIFO and THR to get empty */
94 lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
95 while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
98 serial_console_kick();
101 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
103 switch (serial_console_uart) {
116 static void serial_console_sleep(int enable)
118 if (console_iclk == NULL || console_fclk == NULL)
122 BUG_ON(serial_console_clock_disabled);
123 if (clk_get_usecount(console_fclk) == 0)
125 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
128 clk_disable(console_iclk);
129 clk_disable(console_fclk);
130 serial_console_clock_disabled = 1;
132 int serial_wakeup = 0;
135 switch (serial_console_uart) {
137 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
138 if (l & OMAP24XX_ST_UART1)
142 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
143 if (l & OMAP24XX_ST_UART2)
147 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
148 if (l & OMAP24XX_ST_UART3)
153 serial_console_kick();
154 if (!serial_console_clock_disabled)
156 clk_enable(console_iclk);
157 clk_enable(console_fclk);
158 serial_console_clock_disabled = 0;
162 static void pm_init_serial_console(void)
164 const struct omap_serial_console_config *conf;
168 conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
169 struct omap_serial_console_config);
172 if (conf->console_uart > 3 || conf->console_uart < 1)
174 serial_console_uart = conf->console_uart;
175 sprintf(name, "uart%d_fck", conf->console_uart);
176 console_fclk = clk_get(NULL, name);
177 if (IS_ERR(console_fclk))
180 console_iclk = clk_get(NULL, name);
181 if (IS_ERR(console_fclk))
183 if (console_fclk == NULL || console_iclk == NULL) {
184 serial_console_uart = 0;
187 switch (serial_console_uart) {
189 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
190 l |= OMAP24XX_ST_UART1;
191 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
194 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
195 l |= OMAP24XX_ST_UART2;
196 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
199 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
200 l |= OMAP24XX_ST_UART3;
201 prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
206 #define DUMP_PRM_MOD_REG(mod, reg) \
207 regs[reg_count].name = #mod "." #reg; \
208 regs[reg_count++].val = prm_read_mod_reg(mod, reg)
209 #define DUMP_CM_MOD_REG(mod, reg) \
210 regs[reg_count].name = #mod "." #reg; \
211 regs[reg_count++].val = cm_read_mod_reg(mod, reg)
212 #define DUMP_PRM_REG(reg) \
213 regs[reg_count].name = #reg; \
214 regs[reg_count++].val = prm_read_reg(reg)
215 #define DUMP_CM_REG(reg) \
216 regs[reg_count].name = #reg; \
217 regs[reg_count++].val = cm_read_reg(reg)
218 #define DUMP_INTC_REG(reg, off) \
219 regs[reg_count].name = #reg; \
220 regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
222 static void omap2_pm_dump(int mode, int resume, unsigned int us)
228 int reg_count = 0, i;
229 const char *s1 = NULL, *s2 = NULL;
234 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
235 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
236 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
237 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
238 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
242 DUMP_INTC_REG(INTC_MIR0, 0x0084);
243 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
244 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
247 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
248 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
249 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
250 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
251 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
252 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
253 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
254 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
255 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
256 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
257 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
261 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
262 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
263 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
264 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
265 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
266 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
267 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
268 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
269 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
270 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
273 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
274 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
275 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
276 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
278 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
279 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
280 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
300 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
301 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
302 jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
305 printk("--- Going to %s %s\n", s1, s2);
308 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
309 for (i = 0; i < reg_count; i++)
310 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
314 static inline void serial_console_sleep(int enable) {}
315 static inline void pm_init_serial_console(void) {}
316 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
317 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
319 #define omap2_pm_debug 0
323 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
325 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
327 return sprintf(buf, "%hu\n", enable_dyn_sleep);
330 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
334 unsigned short value;
335 if (sscanf(buf, "%hu", &value) != 1 ||
336 (value != 0 && value != 1)) {
337 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
340 enable_dyn_sleep = value;
344 static struct subsys_attribute sleep_while_idle_attr = {
346 .name = __stringify(sleep_while_idle),
349 .show = omap_pm_sleep_while_idle_show,
350 .store = omap_pm_sleep_while_idle_store,
353 static struct clk *osc_ck, *emul_ck;
355 static int omap2_fclks_active(void)
359 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
360 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
361 serial_console_fclk_mask(&f1, &f2);
367 static int omap2_irq_pending(void)
369 u32 pending_reg = IO_ADDRESS(0x480fe098);
372 for (i = 0; i < 4; i++) {
373 if (__raw_readl(pending_reg))
380 static atomic_t sleep_block = ATOMIC_INIT(0);
382 void omap2_block_sleep(void)
384 atomic_inc(&sleep_block);
387 void omap2_allow_sleep(void)
391 i = atomic_dec_return(&sleep_block);
395 static void omap2_enter_full_retention(void)
397 u32 l, sleep_time = 0;
399 /* There is 1 reference hold for all children of the oscillator
400 * clock, the following will remove it. If no one else uses the
401 * oscillator itself it will be disabled if/when we enter retention
406 /* Clear old wake-up events */
407 /* REVISIT: These write to reserved bits? */
408 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
409 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
410 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
412 /* Try to enter retention */
413 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
414 MPU_MOD, PM_PWSTCTRL);
416 /* Workaround to kill USB */
417 l = ctrl_read_reg(CONTROL_DEVCONF0) | 0x00008000;
418 ctrl_write_reg(l, CONTROL_DEVCONF0);
420 omap2_gpio_prepare_for_retention();
422 if (omap2_pm_debug) {
423 omap2_pm_dump(0, 0, 0);
424 sleep_time = omap2_read_32k_sync_counter();
427 /* One last check for pending IRQs to avoid extra latency due
428 * to sleeping unnecessarily. */
429 if (omap2_irq_pending())
432 serial_console_sleep(1);
433 /* Jump to SRAM suspend code */
434 omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
436 serial_console_sleep(0);
438 if (omap2_pm_debug) {
439 unsigned long long tmp;
442 resume_time = omap2_read_32k_sync_counter();
443 tmp = resume_time - sleep_time;
445 omap2_pm_dump(0, 1, tmp / 32768);
447 omap2_gpio_resume_after_retention();
451 /* clear CORE wake-up events */
452 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
453 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
455 /* wakeup domain events */
456 l = prm_read_mod_reg(WKUP_MOD, PM_WKST);
457 l &= 0x5; /* bit 1: GPT1, bit5 GPIO */
458 prm_write_mod_reg(l, WKUP_MOD, PM_WKST);
460 /* MPU domain wake events */
461 l = prm_read_reg(OMAP24XX_PRCM_IRQSTATUS_MPU);
463 prm_write_reg(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
465 prm_write_reg(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
467 /* Mask future PRCM-to-MPU interrupts */
468 prm_write_reg(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
471 static int omap2_i2c_active(void)
475 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
476 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
479 static int sti_console_enabled;
481 static int omap2_allow_mpu_retention(void)
485 if (atomic_read(&sleep_block))
488 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
489 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
490 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
491 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
492 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
494 /* Check for UART3. */
495 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
496 if (l & OMAP24XX_EN_UART3)
498 if (sti_console_enabled)
504 static void omap2_enter_mpu_retention(void)
509 /* Putting MPU into the WFI state while a transfer is active
510 * seems to cause the I2C block to timeout. Why? Good question. */
511 if (omap2_i2c_active())
514 /* The peripherals seem not to be able to wake up the MPU when
515 * it is in retention mode. */
516 if (omap2_allow_mpu_retention()) {
517 /* REVISIT: These write to reserved bits? */
518 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
519 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
520 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
522 /* Try to enter MPU retention */
523 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
525 MPU_MOD, PM_PWSTCTRL);
527 /* Block MPU retention */
529 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
533 if (omap2_pm_debug) {
534 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
535 sleep_time = omap2_read_32k_sync_counter();
540 if (omap2_pm_debug) {
541 unsigned long long tmp;
544 resume_time = omap2_read_32k_sync_counter();
545 tmp = resume_time - sleep_time;
547 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
551 static int omap2_can_sleep(void)
553 if (!enable_dyn_sleep)
555 if (omap2_fclks_active())
557 if (atomic_read(&sleep_block) > 0)
559 if (clk_get_usecount(osc_ck) > 1)
561 if (omap_dma_running())
567 static void omap2_pm_idle(void)
572 if (!omap2_can_sleep()) {
573 /* timer_dyn_reprogram() takes about 100-200 us to complete.
574 * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
575 * transfer to complete), the increased latency is too much.
577 * omap2_block_sleep() and omap2_allow_sleep() can be used
580 if (atomic_read(&sleep_block) == 0) {
581 timer_dyn_reprogram();
582 if (omap2_irq_pending())
585 omap2_enter_mpu_retention();
590 * Since an interrupt may set up a timer, we don't want to
591 * reprogram the hardware timer with interrupts enabled.
592 * Re-enable interrupts only after returning from idle.
594 timer_dyn_reprogram();
596 if (omap2_irq_pending())
599 omap2_enter_full_retention();
606 static int omap2_pm_prepare(void)
608 /* We cannot sleep in idle until we have resumed */
609 saved_idle = pm_idle;
615 static int omap2_pm_suspend(void)
619 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
620 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
623 mir1 = omap_readl(0x480fe0a4);
624 omap_writel(1 << 5, 0x480fe0ac);
626 omap2_enter_full_retention();
628 omap_writel(mir1, 0x480fe0a4);
629 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
634 static int omap2_pm_enter(suspend_state_t state)
639 case PM_SUSPEND_STANDBY:
641 ret = omap2_pm_suspend();
650 static void omap2_pm_finish(void)
652 pm_idle = saved_idle;
655 static struct platform_suspend_ops omap_pm_ops = {
656 .prepare = omap2_pm_prepare,
657 .enter = omap2_pm_enter,
658 .finish = omap2_pm_finish,
659 .valid = suspend_valid_only_mem,
662 static void __init prcm_setup_regs(void)
666 /* Enable autoidle */
667 prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
669 /* Set all domain wakeup dependencies */
670 prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
671 prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
672 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
673 prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
674 if (cpu_is_omap2430())
675 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
677 l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
678 /* Enable retention for all memory blocks */
679 l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
680 OMAP24XX_MEM1RETSTATE;
682 /* Set power state to RETENTION */
683 l &= ~OMAP_POWERSTATE_MASK;
684 l |= 0x01 << OMAP_POWERSTATE_SHIFT;
685 prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
687 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
689 MPU_MOD, PM_PWSTCTRL);
691 /* Power down DSP and GFX */
692 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
693 OMAP24XX_DSP_MOD, PM_PWSTCTRL);
694 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
695 GFX_MOD, PM_PWSTCTRL);
697 /* Enable clock auto control for all domains */
698 cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
699 cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
700 OMAP24XX_AUTOSTATE_L3,
701 CORE_MOD, CM_CLKSTCTRL);
702 cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
703 cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
704 OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
706 /* Enable clock autoidle for all domains */
707 cm_write_mod_reg(OMAP24XX_AUTO_CAM |
708 OMAP24XX_AUTO_MAILBOXES |
711 OMAP24XX_AUTO_MSPRO |
716 OMAP24XX_AUTO_UART2 |
717 OMAP24XX_AUTO_UART1 |
720 OMAP24XX_AUTO_MCSPI2 |
721 OMAP24XX_AUTO_MCSPI1 |
722 OMAP24XX_AUTO_MCBSP2 |
723 OMAP24XX_AUTO_MCBSP1 |
724 OMAP24XX_AUTO_GPT12 |
725 OMAP24XX_AUTO_GPT11 |
726 OMAP24XX_AUTO_GPT10 |
735 OMAP2420_AUTO_VLYNQ |
737 CORE_MOD, CM_AUTOIDLE1);
738 cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
741 CORE_MOD, CM_AUTOIDLE2);
742 cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
745 CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
746 cm_write_mod_reg(OMAP24XX_AUTO_PKA |
751 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
753 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
755 /* Put DPLL and both APLLs into autoidle mode */
756 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
757 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
758 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
759 PLL_MOD, CM_AUTOIDLE);
761 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
763 OMAP24XX_AUTO_MPU_WDT |
764 OMAP24XX_AUTO_GPIOS |
765 OMAP24XX_AUTO_32KSYNC |
767 WKUP_MOD, CM_AUTOIDLE);
769 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
771 prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
773 /* Configure automatic voltage transition */
774 prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
775 prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
776 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
777 OMAP24XX_MEMRETCTRL |
778 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
779 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
780 OMAP24XX_PRCM_VOLTCTRL);
782 /* Enable wake-up events */
783 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
787 int __init omap2_pm_init(void)
791 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
792 l = prm_read_reg(OMAP24XX_PRCM_REVISION);
793 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
795 osc_ck = clk_get(NULL, "osc_ck");
796 if (IS_ERR(osc_ck)) {
797 printk(KERN_ERR "could not get osc_ck\n");
801 if (cpu_is_omap242x()) {
802 emul_ck = clk_get(NULL, "emul_ck");
803 if (IS_ERR(emul_ck)) {
804 printk(KERN_ERR "could not get emul_ck\n");
812 pm_init_serial_console();
814 /* Hack to prevent MPU retention when STI console is enabled. */
816 const struct omap_sti_console_config *sti;
818 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
819 struct omap_sti_console_config);
820 if (sti != NULL && sti->enable)
821 sti_console_enabled = 1;
825 * We copy the assembler sleep/wakeup routines to SRAM.
826 * These routines need to be in SRAM as that's the only
827 * memory the MPU can see when it wakes up.
829 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
830 omap24xx_idle_loop_suspend_sz);
832 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
833 omap24xx_cpu_suspend_sz);
835 /* Patch in the correct register addresses for multiboot */
836 omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
838 OMAP_SDRC_REGADDR(SDRC_POWER));
839 omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
841 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
843 suspend_set_ops(&omap_pm_ops);
844 pm_idle = omap2_pm_idle;
846 l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
848 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
853 late_initcall(omap2_pm_init);