arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/pm.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/pm.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/sysfs.h>
  29 #include <linux/module.h>
  30 #include <linux/delay.h>
  31 #include <linux/clk.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35 #include <asm/atomic.h>
  36 #include <asm/mach/time.h>
  37 #include <asm/mach/irq.h>
  38 #include <asm/mach-types.h>
  39
  40 #include <asm/arch/irqs.h>
  41 #include <asm/arch/clock.h>
  42 #include <asm/arch/sram.h>
  43 #include <asm/arch/pm.h>
  44 #include <asm/arch/mux.h>
  45 #include <asm/arch/dma.h>
  46 #include <asm/arch/board.h>
  47 #include <asm/arch/gpio.h>
  48
  49 #include "sdrc.h"
  50
  51 #define PRCM_REVISION           0x000
  52 #define PRCM_SYSCONFIG          0x010
  53 #define PRCM_IRQSTATUS_MPU      0x018
  54 #define PRCM_IRQENABLE_MPU      0x01c
  55 #define PRCM_VOLTCTRL           0x050
  56 #define         AUTO_EXTVOLT    (1 << 15)
  57 #define         FORCE_EXTVOLT   (1 << 14)
  58 #define         SETOFF_LEVEL(x) (((x) & 0x3) << 12)
  59 #define         MEMRETCTRL      (1 << 8)
  60 #define         SETRET_LEVEL(x) (((x) & 0x3) << 6)
  61 #define         VOLT_LEVEL(x)   (((x) & 0x3) << 0)
  62 #define PRCM_CLKSRC_CTRL        0x060
  63 #define PRCM_CLKOUT_CTRL        0x070
  64 #define PRCM_CLKEMUL_CTRL       0x078
  65 #define PRCM_CLKCFG_CTRL        0x080
  66 #define PRCM_VOLTSETUP          0x090
  67 #define PRCM_CLKSSETUP          0x094
  68
  69
  70 #define CM_CLKSEL_MPU           0x140
  71 #define CM_CLKSTCTRL_MPU        0x148
  72 #define         AUTOSTAT_MPU    (1 << 0)
  73 #define PM_WKDEP_MPU            0x1c8
  74 #define         EN_WKUP         (1 << 4)
  75 #define         EN_GFX          (1 << 3)
  76 #define         EN_DSP          (1 << 2)
  77 #define         EN_MPU          (1 << 1)
  78 #define         EN_CORE         (1 << 0)
  79 #define PM_PWSTCTRL_MPU         0x1e0
  80 #define PM_PWSTST_MPU           0x1e4
  81
  82
  83 #define CM_FCLKEN1_CORE         0x200
  84 #define CM_FCLKEN2_CORE         0x204
  85 #define CM_ICLKEN1_CORE         0x210
  86 #define CM_ICLKEN2_CORE         0x214
  87 #define CM_ICLKEN4_CORE         0x21c
  88 #define CM_IDLEST1_CORE         0x220
  89 #define CM_IDLEST2_CORE         0x224
  90 #define CM_AUTOIDLE1_CORE       0x230
  91 #define CM_AUTOIDLE2_CORE       0x234
  92 #define CM_AUTOIDLE3_CORE       0x238
  93 #define CM_AUTOIDLE4_CORE       0x23c
  94 #define CM_CLKSEL1_CORE         0x240
  95 #define CM_CLKSEL2_CORE         0x244
  96 #define CM_CLKSTCTRL_CORE       0x248
  97 #define         AUTOSTAT_DSS    (1 << 2)
  98 #define         AUTOSTAT_L4     (1 << 1)
  99 #define         AUTOSTAT_L3     (1 << 0)
 100 #define PM_WKEN1_CORE           0x2a0
 101 #define PM_WKEN2_CORE           0x2a4
 102 #define PM_WKST1_CORE           0x2b0
 103 #define PM_WKST2_CORE           0x2b4
 104 #define PM_WKDEP_CORE           0x2c8
 105 #define PM_PWSTCTRL_CORE        0x2e0
 106 #define PM_PWSTST_CORE          0x2e4
 107
 108
 109 #define CM_CLKSTCTRL_GFX        0x348
 110 #define         AUTOSTAT_GFX    (1 << 0)
 111 #define PM_WKDEP_GFX            0x3c8
 112 #define PM_PWSTCTRL_GFX         0x3e0
 113
 114
 115 #define CM_FCLKEN_WKUP          0x400
 116 #define CM_ICLKEN_WKUP          0x410
 117 #define CM_AUTOIDLE_WKUP        0x430
 118 #define PM_WKEN_WKUP            0x4a0
 119 #define         EN_GPIOS        (1 << 2)
 120 #define         EN_GPT1         (1 << 0)
 121 #define PM_WKST_WKUP            0x4b0
 122
 123
 124 #define CM_CLKEN_PLL            0x500
 125 #define CM_IDLEST_CKGEN         0x520
 126 #define CM_AUTOIDLE_PLL         0x530
 127 #define CM_CLKSEL1_PLL          0x540
 128 #define CM_CLKSEL2_PLL          0x544
 129
 130
 131 #define CM_FCLKEN_DSP           0x800
 132 #define CM_ICLKEN_DSP           0x810
 133 #define CM_IDLEST_DSP           0x820
 134 #define CM_AUTOIDLE_DSP         0x830
 135 #define CM_CLKSEL_DSP           0x840
 136 #define CM_CLKSTCTRL_DSP        0x848
 137 #define         AUTOSTAT_IVA    (1 << 8)
 138 #define         AUTOSTAT_DSP    (1 << 0)
 139 #define RM_RSTCTRL_DSP          0x850
 140 #define RM_RSTST_DSP            0x858
 141 #define PM_WKDEP_DSP            0x8c8
 142 #define PM_PWSTCTRL_DSP         0x8e0
 143 #define PM_PWSTST_DSP           0x8e4
 144
 145 static void (*omap2_sram_idle)(void);
 146 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
 147 static void (*saved_idle)(void);
 148
 149 static u32 prcm_base = IO_ADDRESS(OMAP2_PRCM_BASE);
 150
 151 static inline void prcm_write_reg(int idx, u32 val)
 152 {
 153         __raw_writel(val, prcm_base + idx);
 154 }
 155
 156 static inline u32 prcm_read_reg(int idx)
 157 {
 158         return __raw_readl(prcm_base + idx);
 159 }
 160
 161 static u32 omap2_read_32k_sync_counter(void)
 162 {
 163         return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
 164 }
 165
 166 #ifdef CONFIG_PM_DEBUG
 167 int omap2_pm_debug = 0;
 168
 169 static int serial_console_clock_disabled;
 170 static int serial_console_uart;
 171 static unsigned int serial_console_next_disable;
 172
 173 static struct clk *console_iclk, *console_fclk;
 174
 175 static void serial_console_kick(void)
 176 {
 177         serial_console_next_disable = omap2_read_32k_sync_counter();
 178         /* Keep the clocks on for 4 secs */
 179         serial_console_next_disable += 4 * 32768;
 180 }
 181
 182 static void serial_wait_tx(void)
 183 {
 184         static const unsigned long uart_bases[3] = {
 185                 0x4806a000, 0x4806c000, 0x4806e000
 186         };
 187         unsigned long lsr_reg;
 188         int looped = 0;
 189
 190         /* Wait for TX FIFO and THR to get empty */
 191         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
 192         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
 193                 looped = 1;
 194         if (looped)
 195                 serial_console_kick();
 196 }
 197
 198 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
 199 {
 200         switch (serial_console_uart)  {
 201         case 1:
 202                 *f1 &= ~(1 << 21);
 203                 break;
 204         case 2:
 205                 *f1 &= ~(1 << 22);
 206                 break;
 207         case 3:
 208                 *f2 &= ~(1 << 2);
 209                 break;
 210         }
 211 }
 212
 213 static void serial_console_sleep(int enable)
 214 {
 215         if (console_iclk == NULL || console_fclk == NULL)
 216                 return;
 217
 218         if (enable) {
 219                 BUG_ON(serial_console_clock_disabled);
 220                 if (clk_get_usecount(console_fclk) == 0)
 221                         return;
 222                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 223                         return;
 224                 serial_wait_tx();
 225                 clk_disable(console_iclk);
 226                 clk_disable(console_fclk);
 227                 serial_console_clock_disabled = 1;
 228         } else {
 229                 int serial_wakeup = 0;
 230                 u32 l;
 231
 232                 switch (serial_console_uart)  {
 233                 case 1:
 234                         l = prcm_read_reg(PM_WKST1_CORE);
 235                         if (l & (1 << 21))
 236                                 serial_wakeup = 1;
 237                         break;
 238                 case 2:
 239                         l = prcm_read_reg(PM_WKST1_CORE);
 240                         if (l & (1 << 22))
 241                                 serial_wakeup = 1;
 242                         break;
 243                 case 3:
 244                         l = prcm_read_reg(PM_WKST2_CORE);
 245                         if (l & (1 << 2))
 246                                 serial_wakeup = 1;
 247                         break;
 248                 }
 249                 if (serial_wakeup)
 250                         serial_console_kick();
 251                 if (!serial_console_clock_disabled)
 252                         return;
 253                 clk_enable(console_iclk);
 254                 clk_enable(console_fclk);
 255                 serial_console_clock_disabled = 0;
 256         }
 257 }
 258
 259 static void pm_init_serial_console(void)
 260 {
 261         const struct omap_serial_console_config *conf;
 262         char name[16];
 263         u32 l;
 264
 265         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 266                                struct omap_serial_console_config);
 267         if (conf == NULL)
 268                 return;
 269         if (conf->console_uart > 3 || conf->console_uart < 1)
 270                 return;
 271         serial_console_uart = conf->console_uart;
 272         sprintf(name, "uart%d_fck", conf->console_uart);
 273         console_fclk = clk_get(NULL, name);
 274         if (IS_ERR(console_fclk))
 275                 console_fclk = NULL;
 276         name[6] = 'i';
 277         console_iclk = clk_get(NULL, name);
 278         if (IS_ERR(console_fclk))
 279                 console_iclk = NULL;
 280         if (console_fclk == NULL || console_iclk == NULL) {
 281                 serial_console_uart = 0;
 282                 return;
 283         }
 284         switch (serial_console_uart) {
 285         case 1:
 286                 l = prcm_read_reg(PM_WKEN1_CORE);
 287                 l |= 1 << 21;
 288                 prcm_write_reg(PM_WKEN1_CORE, l);
 289                 break;
 290         case 2:
 291                 l = prcm_read_reg(PM_WKEN1_CORE);
 292                 l |= 1 << 22;
 293                 prcm_write_reg(PM_WKEN1_CORE, l);
 294                 break;
 295         case 3:
 296                 l = prcm_read_reg(PM_WKEN2_CORE);
 297                 l |= 1 << 2;
 298                 prcm_write_reg(PM_WKEN2_CORE, l);
 299                 break;
 300         }
 301 }
 302
 303 #define DUMP_REG(reg) \
 304         regs[reg_count].name = #reg; \
 305         regs[reg_count++].val = prcm_read_reg(reg)
 306 #define DUMP_INTC_REG(reg, off) \
 307         regs[reg_count].name = #reg; \
 308         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 309
 310 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 311 {
 312         struct reg {
 313                 const char *name;
 314                 u32 val;
 315         } regs[32];
 316         int reg_count = 0, i;
 317         const char *s1 = NULL, *s2 = NULL;
 318
 319         if (!resume) {
 320 #if 0
 321                 /* MPU */
 322                 DUMP_REG(PRCM_IRQENABLE_MPU);
 323                 DUMP_REG(CM_CLKSTCTRL_MPU);
 324                 DUMP_REG(PM_PWSTCTRL_MPU);
 325                 DUMP_REG(PM_PWSTST_MPU);
 326                 DUMP_REG(PM_WKDEP_MPU);
 327 #endif
 328 #if 0
 329                 /* INTC */
 330                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 331                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 332                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 333 #endif
 334 #if 0
 335                 DUMP_REG(CM_FCLKEN1_CORE);
 336                 DUMP_REG(CM_FCLKEN2_CORE);
 337                 DUMP_REG(CM_FCLKEN_WKUP);
 338                 DUMP_REG(CM_ICLKEN1_CORE);
 339                 DUMP_REG(CM_ICLKEN2_CORE);
 340                 DUMP_REG(CM_ICLKEN_WKUP);
 341                 DUMP_REG(CM_CLKEN_PLL);
 342                 DUMP_REG(PRCM_CLKEMUL_CTRL);
 343                 DUMP_REG(CM_AUTOIDLE_PLL);
 344                 DUMP_REG(PM_PWSTST_CORE);
 345                 DUMP_REG(PRCM_CLKSRC_CTRL);
 346 #endif
 347 #if 0
 348                 /* DSP */
 349                 DUMP_REG(CM_FCLKEN_DSP);
 350                 DUMP_REG(CM_ICLKEN_DSP);
 351                 DUMP_REG(CM_IDLEST_DSP);
 352                 DUMP_REG(CM_AUTOIDLE_DSP);
 353                 DUMP_REG(CM_CLKSEL_DSP);
 354                 DUMP_REG(CM_CLKSTCTRL_DSP);
 355                 DUMP_REG(RM_RSTCTRL_DSP);
 356                 DUMP_REG(RM_RSTST_DSP);
 357                 DUMP_REG(PM_PWSTCTRL_DSP);
 358                 DUMP_REG(PM_PWSTST_DSP);
 359 #endif
 360         } else {
 361                 DUMP_REG(PM_WKST1_CORE);
 362                 DUMP_REG(PM_WKST2_CORE);
 363                 DUMP_REG(PM_WKST_WKUP);
 364                 DUMP_REG(PRCM_IRQSTATUS_MPU);
 365 #if 1
 366                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 367                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 368                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 369 #endif
 370         }
 371
 372         switch (mode) {
 373         case 0:
 374                 s1 = "full";
 375                 s2 = "retention";
 376                 break;
 377         case 1:
 378                 s1 = "MPU";
 379                 s2 = "retention";
 380                 break;
 381         case 2:
 382                 s1 = "MPU";
 383                 s2 = "idle";
 384                 break;
 385         }
 386
 387         if (!resume)
 388 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 389                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 390                        jiffies_to_msecs(next_timer_interrupt() - jiffies));
 391 #else
 392                 printk("--- Going to %s %s\n", s1, s2);
 393 #endif
 394         else
 395                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 396         for (i = 0; i < reg_count; i++)
 397                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 398 }
 399
 400 #else
 401 static inline void serial_console_sleep(int enable) {}
 402 static inline void pm_init_serial_console(void) {}
 403 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 404 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 405
 406 #define omap2_pm_debug 0
 407
 408 #endif
 409
 410 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 411
 412 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
 413 {
 414         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 415 }
 416
 417 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
 418                                               const char * buf,
 419                                               size_t n)
 420 {
 421         unsigned short value;
 422         if (sscanf(buf, "%hu", &value) != 1 ||
 423             (value != 0 && value != 1)) {
 424                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 425                 return -EINVAL;
 426         }
 427         enable_dyn_sleep = value;
 428         return n;
 429 }
 430
 431 static struct subsys_attribute sleep_while_idle_attr = {
 432         .attr   = {
 433                 .name = __stringify(sleep_while_idle),
 434                 .mode = 0644,
 435         },
 436         .show   = omap_pm_sleep_while_idle_show,
 437         .store  = omap_pm_sleep_while_idle_store,
 438 };
 439
 440 static struct clk *osc_ck, *emul_ck;
 441
 442 #define CONTROL_DEVCONF         __REG32(0x48000274)
 443
 444 static int omap2_fclks_active(void)
 445 {
 446         u32 f1, f2;
 447
 448         f1 = prcm_read_reg(CM_FCLKEN1_CORE);
 449         f2 = prcm_read_reg(CM_FCLKEN2_CORE);
 450         serial_console_fclk_mask(&f1, &f2);
 451         if (f1 | f2)
 452                 return 1;
 453         return 0;
 454 }
 455
 456 static int omap2_irq_pending(void)
 457 {
 458         u32 pending_reg = IO_ADDRESS(0x480fe098);
 459         int i;
 460
 461         for (i = 0; i < 4; i++) {
 462                 if (__raw_readl(pending_reg))
 463                         return 1;
 464                 pending_reg += 0x20;
 465         }
 466         return 0;
 467 }
 468
 469 static atomic_t sleep_block = ATOMIC_INIT(0);
 470
 471 void omap2_block_sleep(void)
 472 {
 473         atomic_inc(&sleep_block);
 474 }
 475
 476 void omap2_allow_sleep(void)
 477 {
 478         int i;
 479
 480         i = atomic_dec_return(&sleep_block);
 481         BUG_ON(i < 0);
 482 }
 483
 484 static void omap2_enter_full_retention(void)
 485 {
 486         u32 sleep_time = 0;
 487
 488         /* There is 1 reference hold for all children of the oscillator
 489          * clock, the following will remove it. If no one else uses the
 490          * oscillator itself it will be disabled if/when we enter retention
 491          * mode.
 492          */
 493         clk_disable(osc_ck);
 494
 495         /* Clear old wake-up events */
 496         prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
 497         prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
 498         prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
 499
 500         /* Try to enter retention */
 501         prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 502
 503         /* Workaround to kill USB */
 504         CONTROL_DEVCONF |= 0x00008000;
 505
 506         omap2_gpio_prepare_for_retention();
 507
 508         if (omap2_pm_debug) {
 509                 omap2_pm_dump(0, 0, 0);
 510                 sleep_time = omap2_read_32k_sync_counter();
 511         }
 512
 513         /* One last check for pending IRQs to avoid extra latency due
 514          * to sleeping unnecessarily. */
 515         if (omap2_irq_pending())
 516                 goto no_sleep;
 517
 518         serial_console_sleep(1);
 519         /* Jump to SRAM suspend code */
 520         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 521 no_sleep:
 522         serial_console_sleep(0);
 523
 524         if (omap2_pm_debug) {
 525                 unsigned long long tmp;
 526                 u32 resume_time;
 527
 528                 resume_time = omap2_read_32k_sync_counter();
 529                 tmp = resume_time - sleep_time;
 530                 tmp *= 1000000;
 531                 omap2_pm_dump(0, 1, tmp / 32768);
 532         }
 533         omap2_gpio_resume_after_retention();
 534
 535         clk_enable(osc_ck);
 536
 537 }
 538
 539 static int omap2_i2c_active(void)
 540 {
 541         u32 l;
 542
 543         l = prcm_read_reg(CM_FCLKEN1_CORE);
 544         return l & ((1 << 19) | (1 << 20));
 545 }
 546
 547 static int sti_console_enabled;
 548
 549 static int omap2_allow_mpu_retention(void)
 550 {
 551         u32 l;
 552
 553         if (atomic_read(&sleep_block))
 554                 return 0;
 555
 556         /* Check for UART2, UART1, McSPI2, McSPI1 and DSS1. */
 557         l = prcm_read_reg(CM_FCLKEN1_CORE);
 558         if (l & 0x04660001)
 559                 return 0;
 560         /* Check for UART3. */
 561         l = prcm_read_reg(CM_FCLKEN2_CORE);
 562         if (l & (1 << 2))
 563                 return 0;
 564         if (sti_console_enabled)
 565                 return 0;
 566
 567         return 1;
 568 }
 569
 570 static void omap2_enter_mpu_retention(void)
 571 {
 572         u32 sleep_time = 0;
 573         int only_idle = 0;
 574
 575         /* Putting MPU into the WFI state while a transfer is active
 576          * seems to cause the I2C block to timeout. Why? Good question. */
 577         if (omap2_i2c_active())
 578                 return;
 579
 580         /* The peripherals seem not to be able to wake up the MPU when
 581          * it is in retention mode. */
 582         if (omap2_allow_mpu_retention()) {
 583                 prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
 584                 prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
 585                 prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
 586
 587                 /* Try to enter MPU retention */
 588                 prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 589         } else {
 590                 /* Block MPU retention */
 591                 prcm_write_reg(PM_PWSTCTRL_MPU, 1 << 2);
 592                 only_idle = 1;
 593         }
 594
 595         if (omap2_pm_debug) {
 596                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 597                 sleep_time = omap2_read_32k_sync_counter();
 598         }
 599
 600         omap2_sram_idle();
 601
 602         if (omap2_pm_debug) {
 603                 unsigned long long tmp;
 604                 u32 resume_time;
 605
 606                 resume_time = omap2_read_32k_sync_counter();
 607                 tmp = resume_time - sleep_time;
 608                 tmp *= 1000000;
 609                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 610         }
 611 }
 612
 613 static int omap2_can_sleep(void)
 614 {
 615         if (!enable_dyn_sleep)
 616                 return 0;
 617         if (omap2_fclks_active())
 618                 return 0;
 619         if (atomic_read(&sleep_block) > 0)
 620                 return 0;
 621         if (clk_get_usecount(osc_ck) > 1)
 622                 return 0;
 623         if (omap_dma_running())
 624                 return 0;
 625
 626         return 1;
 627 }
 628
 629 static void omap2_pm_idle(void)
 630 {
 631         local_irq_disable();
 632         local_fiq_disable();
 633
 634         if (!omap2_can_sleep()) {
 635                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 636                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 637                  * transfer to complete), the increased latency is too much.
 638                  *
 639                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 640                  * to indicate this.
 641                  */
 642                 if (atomic_read(&sleep_block) == 0) {
 643                         timer_dyn_reprogram();
 644                         if (omap2_irq_pending())
 645                                 goto out;
 646                 }
 647                 omap2_enter_mpu_retention();
 648                 goto out;
 649         }
 650
 651         /*
 652          * Since an interrupt may set up a timer, we don't want to
 653          * reprogram the hardware timer with interrupts enabled.
 654          * Re-enable interrupts only after returning from idle.
 655          */
 656         timer_dyn_reprogram();
 657
 658         if (omap2_irq_pending())
 659                 goto out;
 660
 661         omap2_enter_full_retention();
 662
 663 out:
 664         local_fiq_enable();
 665         local_irq_enable();
 666 }
 667
 668 static int omap2_pm_prepare(suspend_state_t state)
 669 {
 670         int error = 0;
 671
 672         /* We cannot sleep in idle until we have resumed */
 673         saved_idle = pm_idle;
 674         pm_idle = NULL;
 675
 676         switch (state) {
 677         case PM_SUSPEND_STANDBY:
 678         case PM_SUSPEND_MEM:
 679                 break;
 680         default:
 681                 return -EINVAL;
 682         }
 683
 684         return error;
 685 }
 686
 687 static int omap2_pm_suspend(void)
 688 {
 689         u32 wken_wkup, mir1;
 690
 691         wken_wkup = prcm_read_reg(PM_WKEN_WKUP);
 692         prcm_write_reg(PM_WKEN_WKUP, wken_wkup & ~EN_GPT1);
 693
 694         /* Mask GPT1 */
 695         mir1 = omap_readl(0x480fe0a4);
 696         omap_writel(1 << 5, 0x480fe0ac);
 697
 698         omap2_enter_full_retention();
 699
 700         omap_writel(mir1, 0x480fe0a4);
 701         prcm_write_reg(PM_WKEN_WKUP, wken_wkup);
 702
 703         return 0;
 704 }
 705
 706 static int omap2_pm_enter(suspend_state_t state)
 707 {
 708         int ret = 0;
 709
 710         switch (state) {
 711         case PM_SUSPEND_STANDBY:
 712         case PM_SUSPEND_MEM:
 713                 ret = omap2_pm_suspend();
 714                 break;
 715         default:
 716                 ret = -EINVAL;
 717         }
 718
 719         return ret;
 720 }
 721
 722 static int omap2_pm_finish(suspend_state_t state)
 723 {
 724         pm_idle = saved_idle;
 725         return 0;
 726 }
 727
 728 static struct pm_ops omap_pm_ops = {
 729         .prepare        = omap2_pm_prepare,
 730         .enter          = omap2_pm_enter,
 731         .finish         = omap2_pm_finish,
 732         .valid          = pm_valid_only_mem,
 733 };
 734
 735 static void __init prcm_setup_regs(void)
 736 {
 737         u32 l;
 738
 739         /* Enable autoidle */
 740         prcm_write_reg(PRCM_SYSCONFIG, 1 << 0);
 741
 742         /* Set all domain wakeup dependencies */
 743         prcm_write_reg(PM_WKDEP_MPU, EN_WKUP);
 744         prcm_write_reg(PM_WKDEP_DSP, 0);
 745         prcm_write_reg(PM_WKDEP_GFX, 0);
 746
 747         l = prcm_read_reg(PM_PWSTCTRL_CORE);
 748         /* Enable retention for all memory blocks */
 749         l |= (1 << 3) | (1 << 4) | (1 << 5);
 750         /* Set power state to RETENTION */
 751         l &= ~0x03;
 752         l |= 0x01 << 0;
 753         prcm_write_reg(PM_PWSTCTRL_CORE, l);
 754
 755         prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 756
 757         /* Power down DSP and GFX */
 758         prcm_write_reg(PM_PWSTCTRL_DSP, (1 << 18) | 0x03);
 759         prcm_write_reg(PM_PWSTCTRL_GFX, (1 << 18) | 0x03);
 760
 761         /* Enable clock auto control for all domains */
 762         prcm_write_reg(CM_CLKSTCTRL_MPU, AUTOSTAT_MPU);
 763         prcm_write_reg(CM_CLKSTCTRL_CORE, AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3);
 764         prcm_write_reg(CM_CLKSTCTRL_GFX, AUTOSTAT_GFX);
 765         prcm_write_reg(CM_CLKSTCTRL_DSP, AUTOSTAT_IVA | AUTOSTAT_DSP);
 766
 767         /* Enable clock autoidle for all domains */
 768         prcm_write_reg(CM_AUTOIDLE1_CORE, 0xfffffff9);
 769         prcm_write_reg(CM_AUTOIDLE2_CORE, 0x07);
 770         prcm_write_reg(CM_AUTOIDLE3_CORE, 0x07);
 771         prcm_write_reg(CM_AUTOIDLE4_CORE, 0x1f);
 772
 773         prcm_write_reg(CM_AUTOIDLE_DSP, 0x02);
 774
 775         /* Put DPLL and both APLLs into autoidle mode */
 776         prcm_write_reg(CM_AUTOIDLE_PLL, (0x03 << 0) | (0x03 << 2) | (0x03 << 6));
 777
 778         prcm_write_reg(CM_AUTOIDLE_WKUP, 0x3f);
 779
 780         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 781          * stabilisation */
 782         prcm_write_reg(PRCM_CLKSSETUP, 15);
 783
 784         /* Configure automatic voltage transition */
 785         prcm_write_reg(PRCM_VOLTSETUP, 2);
 786         l = AUTO_EXTVOLT | SETOFF_LEVEL(1) | MEMRETCTRL | \
 787                 SETRET_LEVEL(1) | VOLT_LEVEL(0);
 788         prcm_write_reg(PRCM_VOLTCTRL, l);
 789
 790         /* Enable wake-up events */
 791         prcm_write_reg(PM_WKEN_WKUP, EN_GPIOS | EN_GPT1);
 792 }
 793
 794 int __init omap2_pm_init(void)
 795 {
 796         u32 l;
 797
 798         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 799         l = prcm_read_reg(PRCM_REVISION);
 800         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 801
 802         osc_ck = clk_get(NULL, "osc_ck");
 803         if (IS_ERR(osc_ck)) {
 804                 printk(KERN_ERR "could not get osc_ck\n");
 805                 return -ENODEV;
 806         }
 807
 808         emul_ck = clk_get(NULL, "emul_ck");
 809         if (IS_ERR(emul_ck)) {
 810                 printk(KERN_ERR "could not get emul_ck\n");
 811                 clk_put(osc_ck);
 812                 return -ENODEV;
 813         }
 814
 815         prcm_setup_regs();
 816
 817         pm_init_serial_console();
 818
 819         /* Hack to prevent MPU retention when STI console is enabled. */
 820         {
 821                 const struct omap_sti_console_config *sti;
 822
 823                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 824                                       struct omap_sti_console_config);
 825                 if (sti != NULL && sti->enable)
 826                         sti_console_enabled = 1;
 827         }
 828
 829         /*
 830          * We copy the assembler sleep/wakeup routines to SRAM.
 831          * These routines need to be in SRAM as that's the only
 832          * memory the MPU can see when it wakes up.
 833          */
 834         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 835                                          omap24xx_idle_loop_suspend_sz);
 836         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 837                                             omap24xx_cpu_suspend_sz);
 838
 839         pm_set_ops(&omap_pm_ops);
 840         pm_idle = omap2_pm_idle;
 841
 842         l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 843         if (l)
 844                 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
 845
 846         return 0;
 847 }
 848
 849 late_initcall(omap2_pm_init);