2 * linux/arch/arm/mach-omap2/pm.c
4 * OMAP2 Power Management Routines
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 * Copyright (C) 2006 Nokia Corporation
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * Amit Kucheria <amit.kucheria@nokia.com>
14 * Igor Stoppa <igor.stoppa@nokia.com>
16 * Based on pm.c for omap1
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
23 #include <linux/suspend.h>
24 #include <linux/sched.h>
25 #include <linux/proc_fs.h>
26 #include <linux/interrupt.h>
27 #include <linux/sysfs.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/atomic.h>
35 #include <asm/mach/time.h>
36 #include <asm/mach/irq.h>
37 #include <asm/mach-types.h>
39 #include <asm/arch/irqs.h>
40 #include <asm/arch/clock.h>
41 #include <asm/arch/sram.h>
42 #include <asm/arch/control.h>
43 #include <asm/arch/gpio.h>
44 #include <asm/arch/pm.h>
45 #include <asm/arch/mux.h>
46 #include <asm/arch/dma.h>
47 #include <asm/arch/board.h>
50 #include "prm_regbits_24xx.h"
52 #include "cm_regbits_24xx.h"
55 /* These addrs are in assembly language code to be patched at runtime */
56 extern void *omap2_ocs_sdrc_power;
57 extern void *omap2_ocs_sdrc_dlla_ctrl;
59 static void (*omap2_sram_idle)(void);
60 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
61 static void (*saved_idle)(void);
63 static u32 omap2_read_32k_sync_counter(void)
65 return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
68 #ifdef CONFIG_PM_DEBUG
69 int omap2_pm_debug = 0;
71 static int serial_console_clock_disabled;
72 static int serial_console_uart;
73 static unsigned int serial_console_next_disable;
75 static struct clk *console_iclk, *console_fclk;
77 static void serial_console_kick(void)
79 serial_console_next_disable = omap2_read_32k_sync_counter();
80 /* Keep the clocks on for 4 secs */
81 serial_console_next_disable += 4 * 32768;
84 static void serial_wait_tx(void)
86 static const unsigned long uart_bases[3] = {
87 0x4806a000, 0x4806c000, 0x4806e000
89 unsigned long lsr_reg;
92 /* Wait for TX FIFO and THR to get empty */
93 lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
94 while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
97 serial_console_kick();
100 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
102 switch (serial_console_uart) {
115 static void serial_console_sleep(int enable)
117 if (console_iclk == NULL || console_fclk == NULL)
121 BUG_ON(serial_console_clock_disabled);
122 if (clk_get_usecount(console_fclk) == 0)
124 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
127 clk_disable(console_iclk);
128 clk_disable(console_fclk);
129 serial_console_clock_disabled = 1;
131 int serial_wakeup = 0;
134 switch (serial_console_uart) {
136 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
137 if (l & OMAP24XX_ST_UART1)
141 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
142 if (l & OMAP24XX_ST_UART2)
146 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
147 if (l & OMAP24XX_ST_UART3)
152 serial_console_kick();
153 if (!serial_console_clock_disabled)
155 clk_enable(console_iclk);
156 clk_enable(console_fclk);
157 serial_console_clock_disabled = 0;
161 static void pm_init_serial_console(void)
163 const struct omap_serial_console_config *conf;
167 conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
168 struct omap_serial_console_config);
171 if (conf->console_uart > 3 || conf->console_uart < 1)
173 serial_console_uart = conf->console_uart;
174 sprintf(name, "uart%d_fck", conf->console_uart);
175 console_fclk = clk_get(NULL, name);
176 if (IS_ERR(console_fclk))
179 console_iclk = clk_get(NULL, name);
180 if (IS_ERR(console_fclk))
182 if (console_fclk == NULL || console_iclk == NULL) {
183 serial_console_uart = 0;
186 switch (serial_console_uart) {
188 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
189 l |= OMAP24XX_ST_UART1;
190 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
193 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
194 l |= OMAP24XX_ST_UART2;
195 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
198 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
199 l |= OMAP24XX_ST_UART3;
200 prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
205 #define DUMP_PRM_MOD_REG(mod, reg) \
206 regs[reg_count].name = #mod "." #reg; \
207 regs[reg_count++].val = prm_read_mod_reg(mod, reg)
208 #define DUMP_CM_MOD_REG(mod, reg) \
209 regs[reg_count].name = #mod "." #reg; \
210 regs[reg_count++].val = cm_read_mod_reg(mod, reg)
211 #define DUMP_PRM_REG(reg) \
212 regs[reg_count].name = #reg; \
213 regs[reg_count++].val = prm_read_reg(reg)
214 #define DUMP_CM_REG(reg) \
215 regs[reg_count].name = #reg; \
216 regs[reg_count++].val = cm_read_reg(reg)
217 #define DUMP_INTC_REG(reg, off) \
218 regs[reg_count].name = #reg; \
219 regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
221 static void omap2_pm_dump(int mode, int resume, unsigned int us)
227 int reg_count = 0, i;
228 const char *s1 = NULL, *s2 = NULL;
233 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
234 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
235 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
236 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
237 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
241 DUMP_INTC_REG(INTC_MIR0, 0x0084);
242 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
243 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
246 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
247 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
248 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
249 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
250 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
251 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
252 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
253 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
254 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
255 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
256 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
260 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
261 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
262 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
263 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
264 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
265 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
266 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
267 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
268 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
269 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
272 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
273 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
274 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
275 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
277 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
278 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
279 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
299 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
300 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
301 jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
304 printk("--- Going to %s %s\n", s1, s2);
307 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
308 for (i = 0; i < reg_count; i++)
309 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
313 static inline void serial_console_sleep(int enable) {}
314 static inline void pm_init_serial_console(void) {}
315 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
316 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
318 #define omap2_pm_debug 0
322 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
324 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
326 return sprintf(buf, "%hu\n", enable_dyn_sleep);
329 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
333 unsigned short value;
334 if (sscanf(buf, "%hu", &value) != 1 ||
335 (value != 0 && value != 1)) {
336 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
339 enable_dyn_sleep = value;
343 static struct subsys_attribute sleep_while_idle_attr = {
345 .name = __stringify(sleep_while_idle),
348 .show = omap_pm_sleep_while_idle_show,
349 .store = omap_pm_sleep_while_idle_store,
352 static struct clk *osc_ck, *emul_ck;
354 static int omap2_fclks_active(void)
358 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
359 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
360 serial_console_fclk_mask(&f1, &f2);
366 static int omap2_irq_pending(void)
368 u32 pending_reg = IO_ADDRESS(0x480fe098);
371 for (i = 0; i < 4; i++) {
372 if (__raw_readl(pending_reg))
379 static atomic_t sleep_block = ATOMIC_INIT(0);
381 void omap2_block_sleep(void)
383 atomic_inc(&sleep_block);
386 void omap2_allow_sleep(void)
390 i = atomic_dec_return(&sleep_block);
394 static void omap2_enter_full_retention(void)
396 u32 l, sleep_time = 0;
398 /* There is 1 reference hold for all children of the oscillator
399 * clock, the following will remove it. If no one else uses the
400 * oscillator itself it will be disabled if/when we enter retention
405 /* Clear old wake-up events */
406 /* REVISIT: These write to reserved bits? */
407 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
408 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
409 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
411 /* Try to enter retention */
412 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
413 MPU_MOD, PM_PWSTCTRL);
415 /* Workaround to kill USB */
416 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
417 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
419 omap2_gpio_prepare_for_retention();
421 if (omap2_pm_debug) {
422 omap2_pm_dump(0, 0, 0);
423 sleep_time = omap2_read_32k_sync_counter();
426 /* One last check for pending IRQs to avoid extra latency due
427 * to sleeping unnecessarily. */
428 if (omap2_irq_pending())
431 serial_console_sleep(1);
432 /* Jump to SRAM suspend code */
433 omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
435 serial_console_sleep(0);
437 if (omap2_pm_debug) {
438 unsigned long long tmp;
441 resume_time = omap2_read_32k_sync_counter();
442 tmp = resume_time - sleep_time;
444 omap2_pm_dump(0, 1, tmp / 32768);
446 omap2_gpio_resume_after_retention();
450 /* clear CORE wake-up events */
451 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
452 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
454 /* wakeup domain events */
455 l = prm_read_mod_reg(WKUP_MOD, PM_WKST);
456 l &= 0x5; /* bit 1: GPT1, bit5 GPIO */
457 prm_write_mod_reg(l, WKUP_MOD, PM_WKST);
459 /* MPU domain wake events */
460 l = prm_read_reg(OMAP24XX_PRCM_IRQSTATUS_MPU);
462 prm_write_reg(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
464 prm_write_reg(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
466 /* Mask future PRCM-to-MPU interrupts */
467 prm_write_reg(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
470 static int omap2_i2c_active(void)
474 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
475 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
478 static int sti_console_enabled;
480 static int omap2_allow_mpu_retention(void)
484 if (atomic_read(&sleep_block))
487 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
488 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
489 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
490 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
491 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
493 /* Check for UART3. */
494 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
495 if (l & OMAP24XX_EN_UART3)
497 if (sti_console_enabled)
503 static void omap2_enter_mpu_retention(void)
508 /* Putting MPU into the WFI state while a transfer is active
509 * seems to cause the I2C block to timeout. Why? Good question. */
510 if (omap2_i2c_active())
513 /* The peripherals seem not to be able to wake up the MPU when
514 * it is in retention mode. */
515 if (omap2_allow_mpu_retention()) {
516 /* REVISIT: These write to reserved bits? */
517 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
518 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
519 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
521 /* Try to enter MPU retention */
522 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
524 MPU_MOD, PM_PWSTCTRL);
526 /* Block MPU retention */
528 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
532 if (omap2_pm_debug) {
533 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
534 sleep_time = omap2_read_32k_sync_counter();
539 if (omap2_pm_debug) {
540 unsigned long long tmp;
543 resume_time = omap2_read_32k_sync_counter();
544 tmp = resume_time - sleep_time;
546 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
550 static int omap2_can_sleep(void)
552 if (!enable_dyn_sleep)
554 if (omap2_fclks_active())
556 if (atomic_read(&sleep_block) > 0)
558 if (clk_get_usecount(osc_ck) > 1)
560 if (omap_dma_running())
566 static void omap2_pm_idle(void)
571 if (!omap2_can_sleep()) {
572 /* timer_dyn_reprogram() takes about 100-200 us to complete.
573 * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
574 * transfer to complete), the increased latency is too much.
576 * omap2_block_sleep() and omap2_allow_sleep() can be used
579 if (atomic_read(&sleep_block) == 0) {
580 timer_dyn_reprogram();
581 if (omap2_irq_pending())
584 omap2_enter_mpu_retention();
589 * Since an interrupt may set up a timer, we don't want to
590 * reprogram the hardware timer with interrupts enabled.
591 * Re-enable interrupts only after returning from idle.
593 timer_dyn_reprogram();
595 if (omap2_irq_pending())
598 omap2_enter_full_retention();
605 static int omap2_pm_prepare(void)
607 /* We cannot sleep in idle until we have resumed */
608 saved_idle = pm_idle;
614 static int omap2_pm_suspend(void)
618 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
619 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
622 mir1 = omap_readl(0x480fe0a4);
623 omap_writel(1 << 5, 0x480fe0ac);
625 omap2_enter_full_retention();
627 omap_writel(mir1, 0x480fe0a4);
628 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
633 static int omap2_pm_enter(suspend_state_t state)
638 case PM_SUSPEND_STANDBY:
640 ret = omap2_pm_suspend();
649 static void omap2_pm_finish(void)
651 pm_idle = saved_idle;
654 static struct platform_suspend_ops omap_pm_ops = {
655 .prepare = omap2_pm_prepare,
656 .enter = omap2_pm_enter,
657 .finish = omap2_pm_finish,
658 .valid = suspend_valid_only_mem,
661 static void __init prcm_setup_regs(void)
665 /* Enable autoidle */
666 prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
668 /* Set all domain wakeup dependencies */
669 prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
670 prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
671 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
672 prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
673 if (cpu_is_omap2430())
674 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
676 l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
677 /* Enable retention for all memory blocks */
678 l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
679 OMAP24XX_MEM1RETSTATE;
681 /* Set power state to RETENTION */
682 l &= ~OMAP_POWERSTATE_MASK;
683 l |= 0x01 << OMAP_POWERSTATE_SHIFT;
684 prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
686 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
688 MPU_MOD, PM_PWSTCTRL);
690 /* Power down DSP and GFX */
691 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
692 OMAP24XX_DSP_MOD, PM_PWSTCTRL);
693 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
694 GFX_MOD, PM_PWSTCTRL);
696 /* Enable clock auto control for all domains */
697 cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
698 cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
699 OMAP24XX_AUTOSTATE_L3,
700 CORE_MOD, CM_CLKSTCTRL);
701 cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
702 cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
703 OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
705 /* Enable clock autoidle for all domains */
706 cm_write_mod_reg(OMAP24XX_AUTO_CAM |
707 OMAP24XX_AUTO_MAILBOXES |
710 OMAP24XX_AUTO_MSPRO |
715 OMAP24XX_AUTO_UART2 |
716 OMAP24XX_AUTO_UART1 |
719 OMAP24XX_AUTO_MCSPI2 |
720 OMAP24XX_AUTO_MCSPI1 |
721 OMAP24XX_AUTO_MCBSP2 |
722 OMAP24XX_AUTO_MCBSP1 |
723 OMAP24XX_AUTO_GPT12 |
724 OMAP24XX_AUTO_GPT11 |
725 OMAP24XX_AUTO_GPT10 |
734 OMAP2420_AUTO_VLYNQ |
736 CORE_MOD, CM_AUTOIDLE1);
737 cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
740 CORE_MOD, CM_AUTOIDLE2);
741 cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
744 CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
745 cm_write_mod_reg(OMAP24XX_AUTO_PKA |
750 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
752 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
754 /* Put DPLL and both APLLs into autoidle mode */
755 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
756 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
757 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
758 PLL_MOD, CM_AUTOIDLE);
760 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
762 OMAP24XX_AUTO_MPU_WDT |
763 OMAP24XX_AUTO_GPIOS |
764 OMAP24XX_AUTO_32KSYNC |
766 WKUP_MOD, CM_AUTOIDLE);
768 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
770 prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
772 /* Configure automatic voltage transition */
773 prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
774 prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
775 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
776 OMAP24XX_MEMRETCTRL |
777 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
778 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
779 OMAP24XX_PRCM_VOLTCTRL);
781 /* Enable wake-up events */
782 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
786 int __init omap2_pm_init(void)
790 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
791 l = prm_read_reg(OMAP24XX_PRCM_REVISION);
792 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
794 osc_ck = clk_get(NULL, "osc_ck");
795 if (IS_ERR(osc_ck)) {
796 printk(KERN_ERR "could not get osc_ck\n");
800 if (cpu_is_omap242x()) {
801 emul_ck = clk_get(NULL, "emul_ck");
802 if (IS_ERR(emul_ck)) {
803 printk(KERN_ERR "could not get emul_ck\n");
811 pm_init_serial_console();
813 /* Hack to prevent MPU retention when STI console is enabled. */
815 const struct omap_sti_console_config *sti;
817 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
818 struct omap_sti_console_config);
819 if (sti != NULL && sti->enable)
820 sti_console_enabled = 1;
824 * We copy the assembler sleep/wakeup routines to SRAM.
825 * These routines need to be in SRAM as that's the only
826 * memory the MPU can see when it wakes up.
828 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
829 omap24xx_idle_loop_suspend_sz);
831 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
832 omap24xx_cpu_suspend_sz);
834 /* Patch in the correct register addresses for multiboot */
835 omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
837 OMAP_SDRC_REGADDR(SDRC_POWER));
838 omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
840 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
842 suspend_set_ops(&omap_pm_ops);
843 pm_idle = omap2_pm_idle;
845 l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
847 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
852 late_initcall(omap2_pm_init);