arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006-2008 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/suspend.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32 #include <linux/irq.h>
  33
  34 #include <asm/atomic.h>
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <asm/arch/irqs.h>
  40 #include <asm/arch/clock.h>
  41 #include <asm/arch/sram.h>
  42 #include <asm/arch/control.h>
  43 #include <asm/arch/gpio.h>
  44 #include <asm/arch/pm.h>
  45 #include <asm/arch/mux.h>
  46 #include <asm/arch/dma.h>
  47 #include <asm/arch/board.h>
  48
  49 #include "prm.h"
  50 #include "prm-regbits-24xx.h"
  51 #include "cm.h"
  52 #include "cm-regbits-24xx.h"
  53 #include "sdrc.h"
  54 #include "pm.h"
  55
  56 /* These addrs are in assembly language code to be patched at runtime */
  57 extern void *omap2_ocs_sdrc_power;
  58 extern void *omap2_ocs_sdrc_dlla_ctrl;
  59
  60 static void (*omap2_sram_idle)(void);
  61 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  62 static void (*saved_idle)(void);
  63
  64 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
  65
  66 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
  67                          char *buf)
  68 {
  69         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  70 }
  71
  72 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
  73                           const char *buf, size_t n)
  74 {
  75         unsigned short value;
  76         if (sscanf(buf, "%hu", &value) != 1 ||
  77             (value != 0 && value != 1)) {
  78                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  79                 return -EINVAL;
  80         }
  81         enable_dyn_sleep = value;
  82         return n;
  83 }
  84
  85 static struct kobj_attribute sleep_while_idle_attr =
  86         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
  87
  88 static struct clk *osc_ck, *emul_ck;
  89
  90 static int omap2_fclks_active(void)
  91 {
  92         u32 f1, f2;
  93
  94         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  95         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  96         serial_console_fclk_mask(&f1, &f2);
  97         if (f1 | f2)
  98                 return 1;
  99         return 0;
 100 }
 101
 102 static int omap2_irq_pending(void)
 103 {
 104         u32 pending_reg = 0x480fe098;
 105         int i;
 106
 107         for (i = 0; i < 4; i++) {
 108                 if (omap_readl(pending_reg))
 109                         return 1;
 110                 pending_reg += 0x20;
 111         }
 112         return 0;
 113 }
 114
 115 static atomic_t sleep_block = ATOMIC_INIT(0);
 116
 117 void omap2_block_sleep(void)
 118 {
 119         atomic_inc(&sleep_block);
 120 }
 121
 122 void omap2_allow_sleep(void)
 123 {
 124         int i;
 125
 126         i = atomic_dec_return(&sleep_block);
 127         BUG_ON(i < 0);
 128 }
 129
 130 static void omap2_enter_full_retention(void)
 131 {
 132         u32 l, sleep_time = 0;
 133
 134         /* There is 1 reference hold for all children of the oscillator
 135          * clock, the following will remove it. If no one else uses the
 136          * oscillator itself it will be disabled if/when we enter retention
 137          * mode.
 138          */
 139         clk_disable(osc_ck);
 140
 141         /* Clear old wake-up events */
 142         /* REVISIT: These write to reserved bits? */
 143         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 144         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 145         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 146
 147         /* Try to enter retention */
 148         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
 149                           MPU_MOD, PM_PWSTCTRL);
 150
 151         /* Workaround to kill USB */
 152         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 153         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 154
 155         omap2_gpio_prepare_for_retention();
 156
 157         if (omap2_pm_debug) {
 158                 omap2_pm_dump(0, 0, 0);
 159                 sleep_time = omap2_read_32k_sync_counter();
 160         }
 161
 162         /* One last check for pending IRQs to avoid extra latency due
 163          * to sleeping unnecessarily. */
 164         if (omap2_irq_pending())
 165                 goto no_sleep;
 166
 167         serial_console_sleep(1);
 168         /* Jump to SRAM suspend code */
 169         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 170 no_sleep:
 171         serial_console_sleep(0);
 172
 173         if (omap2_pm_debug) {
 174                 unsigned long long tmp;
 175                 u32 resume_time;
 176
 177                 resume_time = omap2_read_32k_sync_counter();
 178                 tmp = resume_time - sleep_time;
 179                 tmp *= 1000000;
 180                 omap2_pm_dump(0, 1, tmp / 32768);
 181         }
 182         omap2_gpio_resume_after_retention();
 183
 184         clk_enable(osc_ck);
 185
 186         /* clear CORE wake-up events */
 187         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 188         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 189
 190         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 191         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 192
 193         /* MPU domain wake events */
 194         l = __raw_readl(OMAP24XX_PRCM_IRQSTATUS_MPU);
 195         if (l & 0x01)
 196                 __raw_writel(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
 197         if (l & 0x20)
 198                 __raw_writel(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
 199
 200         /* Mask future PRCM-to-MPU interrupts */
 201         __raw_writel(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
 202 }
 203
 204 static int omap2_i2c_active(void)
 205 {
 206         u32 l;
 207
 208         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 209         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 210 }
 211
 212 static int sti_console_enabled;
 213
 214 static int omap2_allow_mpu_retention(void)
 215 {
 216         u32 l;
 217
 218         if (atomic_read(&sleep_block))
 219                 return 0;
 220
 221         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 222         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 223         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 224                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 225                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 226                 return 0;
 227         /* Check for UART3. */
 228         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 229         if (l & OMAP24XX_EN_UART3)
 230                 return 0;
 231         if (sti_console_enabled)
 232                 return 0;
 233
 234         return 1;
 235 }
 236
 237 static void omap2_enter_mpu_retention(void)
 238 {
 239         u32 sleep_time = 0;
 240         int only_idle = 0;
 241
 242         /* Putting MPU into the WFI state while a transfer is active
 243          * seems to cause the I2C block to timeout. Why? Good question. */
 244         if (omap2_i2c_active())
 245                 return;
 246
 247         /* The peripherals seem not to be able to wake up the MPU when
 248          * it is in retention mode. */
 249         if (omap2_allow_mpu_retention()) {
 250                 /* REVISIT: These write to reserved bits? */
 251                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 252                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 253                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 254
 255                 /* Try to enter MPU retention */
 256                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 257                                   OMAP_LOGICRETSTATE,
 258                                   MPU_MOD, PM_PWSTCTRL);
 259         } else {
 260                 /* Block MPU retention */
 261
 262                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 263                 only_idle = 1;
 264         }
 265
 266         if (omap2_pm_debug) {
 267                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 268                 sleep_time = omap2_read_32k_sync_counter();
 269         }
 270
 271         omap2_sram_idle();
 272
 273         if (omap2_pm_debug) {
 274                 unsigned long long tmp;
 275                 u32 resume_time;
 276
 277                 resume_time = omap2_read_32k_sync_counter();
 278                 tmp = resume_time - sleep_time;
 279                 tmp *= 1000000;
 280                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 281         }
 282 }
 283
 284 static int omap2_can_sleep(void)
 285 {
 286         if (!enable_dyn_sleep)
 287                 return 0;
 288         if (omap2_fclks_active())
 289                 return 0;
 290         if (atomic_read(&sleep_block) > 0)
 291                 return 0;
 292         if (clk_get_usecount(osc_ck) > 1)
 293                 return 0;
 294         if (omap_dma_running())
 295                 return 0;
 296
 297         return 1;
 298 }
 299
 300 static void omap2_pm_idle(void)
 301 {
 302         local_irq_disable();
 303         local_fiq_disable();
 304
 305         if (!omap2_can_sleep()) {
 306                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 307                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 308                  * transfer to complete), the increased latency is too much.
 309                  *
 310                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 311                  * to indicate this.
 312                  */
 313                 if (atomic_read(&sleep_block) == 0) {
 314                         timer_dyn_reprogram();
 315                         if (omap2_irq_pending())
 316                                 goto out;
 317                 }
 318                 omap2_enter_mpu_retention();
 319                 goto out;
 320         }
 321
 322         /*
 323          * Since an interrupt may set up a timer, we don't want to
 324          * reprogram the hardware timer with interrupts enabled.
 325          * Re-enable interrupts only after returning from idle.
 326          */
 327         timer_dyn_reprogram();
 328
 329         if (omap2_irq_pending())
 330                 goto out;
 331
 332         omap2_enter_full_retention();
 333
 334 out:
 335         local_fiq_enable();
 336         local_irq_enable();
 337 }
 338
 339 static int omap2_pm_prepare(void)
 340 {
 341         /* We cannot sleep in idle until we have resumed */
 342         saved_idle = pm_idle;
 343         pm_idle = NULL;
 344
 345         return 0;
 346 }
 347
 348 static int omap2_pm_suspend(void)
 349 {
 350         u32 wken_wkup, mir1;
 351
 352         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 353         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 354
 355         /* Mask GPT1 */
 356         mir1 = omap_readl(0x480fe0a4);
 357         omap_writel(1 << 5, 0x480fe0ac);
 358
 359         omap2_enter_full_retention();
 360
 361         omap_writel(mir1, 0x480fe0a4);
 362         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 363
 364         return 0;
 365 }
 366
 367 static int omap2_pm_enter(suspend_state_t state)
 368 {
 369         int ret = 0;
 370
 371         switch (state) {
 372         case PM_SUSPEND_STANDBY:
 373         case PM_SUSPEND_MEM:
 374                 ret = omap2_pm_suspend();
 375                 break;
 376         default:
 377                 ret = -EINVAL;
 378         }
 379
 380         return ret;
 381 }
 382
 383 static void omap2_pm_finish(void)
 384 {
 385         pm_idle = saved_idle;
 386 }
 387
 388 static struct platform_suspend_ops omap_pm_ops = {
 389         .prepare        = omap2_pm_prepare,
 390         .enter          = omap2_pm_enter,
 391         .finish         = omap2_pm_finish,
 392         .valid          = suspend_valid_only_mem,
 393 };
 394
 395 static void __init prcm_setup_regs(void)
 396 {
 397         u32 l;
 398
 399         /* Enable autoidle */
 400         __raw_writel(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 401
 402         /* Set all domain wakeup dependencies */
 403         prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
 404         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 405         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 406         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 407         if (cpu_is_omap2430())
 408                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 409
 410         l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 411         /* Enable retention for all memory blocks */
 412         l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
 413                 OMAP24XX_MEM1RETSTATE;
 414
 415         /* Set power state to RETENTION */
 416         l &= ~OMAP_POWERSTATE_MASK;
 417         l |= 0x01 << OMAP_POWERSTATE_SHIFT;
 418         prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
 419
 420         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 421                           OMAP_LOGICRETSTATE,
 422                           MPU_MOD, PM_PWSTCTRL);
 423
 424         /* Power down DSP and GFX */
 425         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 426                           OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 427         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 428                           GFX_MOD, PM_PWSTCTRL);
 429
 430         /* Enable clock auto control for all domains */
 431         cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU_MASK, MPU_MOD, CM_CLKSTCTRL);
 432         cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS_MASK |
 433                          OMAP24XX_AUTOSTATE_L4_MASK |
 434                          OMAP24XX_AUTOSTATE_L3_MASK,
 435                          CORE_MOD, CM_CLKSTCTRL);
 436         cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX_MASK, GFX_MOD, CM_CLKSTCTRL);
 437         cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA_MASK |
 438                          OMAP24XX_AUTOSTATE_DSP_MASK,
 439                          OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 440
 441         /* Enable clock autoidle for all domains */
 442         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 443                          OMAP24XX_AUTO_MAILBOXES |
 444                          OMAP24XX_AUTO_WDT4 |
 445                          OMAP2420_AUTO_WDT3 |
 446                          OMAP24XX_AUTO_MSPRO |
 447                          OMAP2420_AUTO_MMC |
 448                          OMAP24XX_AUTO_FAC |
 449                          OMAP2420_AUTO_EAC |
 450                          OMAP24XX_AUTO_HDQ |
 451                          OMAP24XX_AUTO_UART2 |
 452                          OMAP24XX_AUTO_UART1 |
 453                          OMAP24XX_AUTO_I2C2 |
 454                          OMAP24XX_AUTO_I2C1 |
 455                          OMAP24XX_AUTO_MCSPI2 |
 456                          OMAP24XX_AUTO_MCSPI1 |
 457                          OMAP24XX_AUTO_MCBSP2 |
 458                          OMAP24XX_AUTO_MCBSP1 |
 459                          OMAP24XX_AUTO_GPT12 |
 460                          OMAP24XX_AUTO_GPT11 |
 461                          OMAP24XX_AUTO_GPT10 |
 462                          OMAP24XX_AUTO_GPT9 |
 463                          OMAP24XX_AUTO_GPT8 |
 464                          OMAP24XX_AUTO_GPT7 |
 465                          OMAP24XX_AUTO_GPT6 |
 466                          OMAP24XX_AUTO_GPT5 |
 467                          OMAP24XX_AUTO_GPT4 |
 468                          OMAP24XX_AUTO_GPT3 |
 469                          OMAP24XX_AUTO_GPT2 |
 470                          OMAP2420_AUTO_VLYNQ |
 471                          OMAP24XX_AUTO_DSS,
 472                          CORE_MOD, CM_AUTOIDLE1);
 473         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 474                          OMAP24XX_AUTO_SSI |
 475                          OMAP24XX_AUTO_USB,
 476                          CORE_MOD, CM_AUTOIDLE2);
 477         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 478                          OMAP24XX_AUTO_GPMC |
 479                          OMAP24XX_AUTO_SDMA,
 480                          CORE_MOD, CM_AUTOIDLE3);
 481         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 482                          OMAP24XX_AUTO_AES |
 483                          OMAP24XX_AUTO_RNG |
 484                          OMAP24XX_AUTO_SHA |
 485                          OMAP24XX_AUTO_DES,
 486                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 487
 488         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 489
 490         /* Put DPLL and both APLLs into autoidle mode */
 491         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 492                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 493                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 494                          PLL_MOD, CM_AUTOIDLE);
 495
 496         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 497                          OMAP24XX_AUTO_WDT1 |
 498                          OMAP24XX_AUTO_MPU_WDT |
 499                          OMAP24XX_AUTO_GPIOS |
 500                          OMAP24XX_AUTO_32KSYNC |
 501                          OMAP24XX_AUTO_GPT1,
 502                          WKUP_MOD, CM_AUTOIDLE);
 503
 504         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 505          * stabilisation */
 506         __raw_writel(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 507
 508         /* Configure automatic voltage transition */
 509         __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 510         __raw_writel(OMAP24XX_AUTO_EXTVOLT |
 511                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 512                       OMAP24XX_MEMRETCTRL |
 513                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 514                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 515                       OMAP24XX_PRCM_VOLTCTRL);
 516
 517         /* Enable wake-up events */
 518         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 519                           WKUP_MOD, PM_WKEN);
 520 }
 521
 522 static int __init omap2_pm_init(void)
 523 {
 524         u32 l;
 525         int error;
 526
 527         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 528         l = __raw_readl(OMAP24XX_PRCM_REVISION);
 529         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 530
 531         osc_ck = clk_get(NULL, "osc_ck");
 532         if (IS_ERR(osc_ck)) {
 533                 printk(KERN_ERR "could not get osc_ck\n");
 534                 return -ENODEV;
 535         }
 536
 537         if (cpu_is_omap242x()) {
 538                 emul_ck = clk_get(NULL, "emul_ck");
 539                 if (IS_ERR(emul_ck)) {
 540                         printk(KERN_ERR "could not get emul_ck\n");
 541                         clk_put(osc_ck);
 542                         return -ENODEV;
 543                 }
 544         }
 545
 546         prcm_setup_regs();
 547
 548         pm_init_serial_console();
 549
 550         /* Hack to prevent MPU retention when STI console is enabled. */
 551         {
 552                 const struct omap_sti_console_config *sti;
 553
 554                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 555                                       struct omap_sti_console_config);
 556                 if (sti != NULL && sti->enable)
 557                         sti_console_enabled = 1;
 558         }
 559
 560         /*
 561          * We copy the assembler sleep/wakeup routines to SRAM.
 562          * These routines need to be in SRAM as that's the only
 563          * memory the MPU can see when it wakes up.
 564          */
 565         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 566                                          omap24xx_idle_loop_suspend_sz);
 567
 568         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 569                                             omap24xx_cpu_suspend_sz);
 570
 571         /* Patch in the correct register addresses for multiboot */
 572         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
 573                            omap2_sram_suspend,
 574                            OMAP_SDRC_REGADDR(SDRC_POWER));
 575         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
 576                            omap2_sram_suspend,
 577                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 578
 579         suspend_set_ops(&omap_pm_ops);
 580         pm_idle = omap2_pm_idle;
 581
 582         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
 583         if (error)
 584                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 585
 586         return 0;
 587 }
 588
 589 late_initcall(omap2_pm_init);