2 * linux/arch/arm/mach-pxa/gpio.c
4 * Generic PXA GPIO handling
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/irq.h>
18 #include <linux/sysdev.h>
21 #include <asm/hardware.h>
23 #include <asm/arch/pxa-regs.h>
28 struct pxa_gpio_chip {
29 struct gpio_chip chip;
30 void __iomem *regbase;
36 * Configure pins for GPIO or other functions
38 int pxa_gpio_mode(int gpio_mode)
41 int gpio = gpio_mode & GPIO_MD_MASK_NR;
42 int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
45 if (gpio > pxa_last_gpio)
48 local_irq_save(flags);
49 if (gpio_mode & GPIO_DFLT_LOW)
50 GPCR(gpio) = GPIO_bit(gpio);
51 else if (gpio_mode & GPIO_DFLT_HIGH)
52 GPSR(gpio) = GPIO_bit(gpio);
53 if (gpio_mode & GPIO_MD_MASK_DIR)
54 GPDR(gpio) |= GPIO_bit(gpio);
56 GPDR(gpio) &= ~GPIO_bit(gpio);
57 gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
58 GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
59 local_irq_restore(flags);
63 EXPORT_SYMBOL(pxa_gpio_mode);
65 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
68 u32 mask = 1 << offset;
70 struct pxa_gpio_chip *pxa;
73 pxa = container_of(chip, struct pxa_gpio_chip, chip);
74 gpdr = pxa->regbase + GPDR_OFFSET;
75 local_irq_save(flags);
76 value = __raw_readl(gpdr);
78 __raw_writel(value, gpdr);
79 local_irq_restore(flags);
84 static int pxa_gpio_direction_output(struct gpio_chip *chip,
85 unsigned offset, int value)
88 u32 mask = 1 << offset;
90 struct pxa_gpio_chip *pxa;
93 pxa = container_of(chip, struct pxa_gpio_chip, chip);
95 pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
96 gpdr = pxa->regbase + GPDR_OFFSET;
97 local_irq_save(flags);
98 tmp = __raw_readl(gpdr);
100 __raw_writel(tmp, gpdr);
101 local_irq_restore(flags);
109 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
111 u32 mask = 1 << offset;
112 struct pxa_gpio_chip *pxa;
114 pxa = container_of(chip, struct pxa_gpio_chip, chip);
115 return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
119 * Set output GPIO level
121 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
123 u32 mask = 1 << offset;
124 struct pxa_gpio_chip *pxa;
126 pxa = container_of(chip, struct pxa_gpio_chip, chip);
129 __raw_writel(mask, pxa->regbase + GPSR_OFFSET);
131 __raw_writel(mask, pxa->regbase + GPCR_OFFSET);
134 #define GPIO_CHIP(_n) \
136 .regbase = GPIO##_n##_BASE, \
138 .label = "gpio-" #_n, \
139 .direction_input = pxa_gpio_direction_input, \
140 .direction_output = pxa_gpio_direction_output, \
141 .get = pxa_gpio_get, \
142 .set = pxa_gpio_set, \
148 static struct pxa_gpio_chip pxa_gpio_chip[] = {
152 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
158 * PXA GPIO edge detection for IRQs:
159 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
160 * Use this instead of directly setting GRER/GFER.
163 static long GPIO_IRQ_rising_edge[4];
164 static long GPIO_IRQ_falling_edge[4];
165 static long GPIO_IRQ_mask[4];
168 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
169 * function of a GPIO, and GPDRx cannot be altered once configured. It
170 * is attributed as "occupied" here (I know this terminology isn't
171 * accurate, you are welcome to propose a better one :-)
173 static int __gpio_is_occupied(unsigned gpio)
175 if (cpu_is_pxa25x() || cpu_is_pxa27x())
176 return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2));
181 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
185 gpio = IRQ_TO_GPIO(irq);
188 if (type == IRQ_TYPE_PROBE) {
189 /* Don't mess with enabled GPIOs using preconfigured edges or
190 * GPIOs set to alternate function or to output during probe
192 if ((GPIO_IRQ_rising_edge[idx] |
193 GPIO_IRQ_falling_edge[idx] |
194 GPDR(gpio)) & GPIO_bit(gpio))
197 if (__gpio_is_occupied(gpio))
200 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
203 GPDR(gpio) &= ~GPIO_bit(gpio);
205 if (type & IRQ_TYPE_EDGE_RISING)
206 __set_bit(gpio, GPIO_IRQ_rising_edge);
208 __clear_bit(gpio, GPIO_IRQ_rising_edge);
210 if (type & IRQ_TYPE_EDGE_FALLING)
211 __set_bit(gpio, GPIO_IRQ_falling_edge);
213 __clear_bit(gpio, GPIO_IRQ_falling_edge);
215 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
216 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
218 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
219 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
220 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
225 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
228 static void pxa_ack_low_gpio(unsigned int irq)
230 GEDR0 = (1 << (irq - IRQ_GPIO0));
233 static void pxa_mask_low_gpio(unsigned int irq)
235 ICMR &= ~(1 << (irq - PXA_IRQ(0)));
238 static void pxa_unmask_low_gpio(unsigned int irq)
240 ICMR |= 1 << (irq - PXA_IRQ(0));
243 static struct irq_chip pxa_low_gpio_chip = {
245 .ack = pxa_ack_low_gpio,
246 .mask = pxa_mask_low_gpio,
247 .unmask = pxa_unmask_low_gpio,
248 .set_type = pxa_gpio_irq_type,
252 * Demux handler for GPIO>=2 edge detect interrupts
255 #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
257 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
260 unsigned long gedr[4];
263 gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
264 gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
265 gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
266 gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
268 GEDR0 = gedr[0]; GEDR1 = gedr[1];
269 GEDR2 = gedr[2]; GEDR3 = gedr[3];
272 bit = find_first_bit(gedr, GEDR_BITS);
273 while (bit < GEDR_BITS) {
276 n = PXA_GPIO_IRQ_BASE + bit;
277 desc_handle_irq(n, irq_desc + n);
279 bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
284 static void pxa_ack_muxed_gpio(unsigned int irq)
286 int gpio = irq - IRQ_GPIO(2) + 2;
287 GEDR(gpio) = GPIO_bit(gpio);
290 static void pxa_mask_muxed_gpio(unsigned int irq)
292 int gpio = irq - IRQ_GPIO(2) + 2;
293 __clear_bit(gpio, GPIO_IRQ_mask);
294 GRER(gpio) &= ~GPIO_bit(gpio);
295 GFER(gpio) &= ~GPIO_bit(gpio);
298 static void pxa_unmask_muxed_gpio(unsigned int irq)
300 int gpio = irq - IRQ_GPIO(2) + 2;
302 __set_bit(gpio, GPIO_IRQ_mask);
303 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
304 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
307 static struct irq_chip pxa_muxed_gpio_chip = {
309 .ack = pxa_ack_muxed_gpio,
310 .mask = pxa_mask_muxed_gpio,
311 .unmask = pxa_unmask_muxed_gpio,
312 .set_type = pxa_gpio_irq_type,
315 void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
319 pxa_last_gpio = gpio_nr - 1;
321 /* clear all GPIO edge detects */
322 for (i = 0; i < gpio_nr; i += 32) {
328 /* GPIO 0 and 1 must have their mask bit always set */
329 GPIO_IRQ_mask[0] = 3;
331 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
332 set_irq_chip(irq, &pxa_low_gpio_chip);
333 set_irq_handler(irq, handle_edge_irq);
334 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
337 for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
338 set_irq_chip(irq, &pxa_muxed_gpio_chip);
339 set_irq_handler(irq, handle_edge_irq);
340 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
343 /* Install handler for GPIO>=2 edge detect interrupts */
344 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
346 pxa_low_gpio_chip.set_wake = fn;
347 pxa_muxed_gpio_chip.set_wake = fn;
349 /* add a GPIO chip for each register bank.
350 * the last PXA25x register only contains 21 GPIOs
352 for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
353 if (gpio + 32 > gpio_nr)
354 pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
355 gpiochip_add(&pxa_gpio_chip[i].chip);
361 static unsigned long saved_gplr[4];
362 static unsigned long saved_gpdr[4];
363 static unsigned long saved_grer[4];
364 static unsigned long saved_gfer[4];
366 static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
370 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
371 saved_gplr[i] = GPLR(gpio);
372 saved_gpdr[i] = GPDR(gpio);
373 saved_grer[i] = GRER(gpio);
374 saved_gfer[i] = GFER(gpio);
376 /* Clear GPIO transition detect bits */
377 GEDR(gpio) = GEDR(gpio);
382 static int pxa_gpio_resume(struct sys_device *dev)
386 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
387 /* restore level with set/clear */
388 GPSR(gpio) = saved_gplr[i];
389 GPCR(gpio) = ~saved_gplr[i];
391 GRER(gpio) = saved_grer[i];
392 GFER(gpio) = saved_gfer[i];
393 GPDR(gpio) = saved_gpdr[i];
398 #define pxa_gpio_suspend NULL
399 #define pxa_gpio_resume NULL
402 struct sysdev_class pxa_gpio_sysclass = {
404 .suspend = pxa_gpio_suspend,
405 .resume = pxa_gpio_resume,
408 static int __init pxa_gpio_init(void)
410 return sysdev_class_register(&pxa_gpio_sysclass);
413 core_initcall(pxa_gpio_init);