2 * arch/arm/mach-pxa/include/mach/dma.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #ifndef __ASM_ARCH_DMA_H
13 #define __ASM_ARCH_DMA_H
15 #include <mach/hardware.h>
17 /* DMA Controller Registers Definitions */
18 #define DMAC_REGS_VIRT io_p2v(0x40000000)
19 #define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
21 #define DCSR(n) DMAC_REG((n) << 2)
22 #define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */
23 #define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */
24 #define DDADR(n) DMAC_REG(0x0200 + ((n) << 4))
25 #define DSADR(n) DMAC_REG(0x0204 + ((n) << 4))
26 #define DTADR(n) DMAC_REG(0x0208 + ((n) << 4))
27 #define DCMD(n) DMAC_REG(0x020c + ((n) << 4))
28 #define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
31 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
32 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
33 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
34 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
35 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
36 #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
37 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
38 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
40 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
41 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
42 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
43 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
44 #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
45 #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
46 #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
47 #define DCSR_EORINTR (1 << 9) /* The end of Receive */
50 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
51 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
53 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
54 #define DDADR_STOP (1 << 0) /* Stop (read / write) */
56 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
57 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
58 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
59 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
60 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
61 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
62 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
63 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
64 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
65 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
66 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
67 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
68 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
69 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
72 * Descriptor structure for PXA's DMA engine
73 * Note: this structure must always be aligned to a 16-byte boundary.
76 typedef struct pxa_dma_desc {
77 volatile u32 ddadr; /* Points to the next descriptor + flags */
78 volatile u32 dsadr; /* DSADR value for the current transfer */
79 volatile u32 dtadr; /* DTADR value for the current transfer */
80 volatile u32 dcmd; /* DCMD value for the current transfer */
93 int __init pxa_init_dma(int irq, int num_ch);
95 int pxa_request_dma (char *name,
97 void (*irq_handler)(int, void *),
100 void pxa_free_dma (int dma_ch);
102 #endif /* _ASM_ARCH_DMA_H */