1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor"
19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
22 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc.
25 Say Y if you want support for the ARM610 processor.
30 bool "Support ARM7TDMI processor"
35 A 32-bit RISC microprocessor based on the ARM7 processor core
36 which has no memory control unit and cache.
38 Say Y if you want support for the ARM7TDMI processor.
43 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
44 default y if ARCH_CLPS7500
49 select CPU_COPY_V3 if MMU
50 select CPU_TLB_V3 if MMU
52 A 32-bit RISC microprocessor based on the ARM7 processor core
53 designed by Advanced RISC Machines Ltd. The ARM710 is the
54 successor to the ARM610 processor. It was released in
55 July 1994 by VLSI Technology Inc.
57 Say Y if you want support for the ARM710 processor.
62 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
63 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
69 select CPU_COPY_V4WT if MMU
70 select CPU_TLB_V4WT if MMU
72 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
73 MMU built around an ARM7TDMI core.
75 Say Y if you want support for the ARM720T processor.
80 bool "Support ARM740T processor" if ARCH_INTEGRATOR
83 select CPU_CACHE_V3 # although the core is v4t
86 A 32-bit RISC processor with 8KB cache or 4KB variants,
87 write buffer and MPU(Protection Unit) built around
90 Say Y if you want support for the ARM740T processor.
95 bool "Support ARM920T processor"
96 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
97 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
100 select CPU_CACHE_V4WT
101 select CPU_CACHE_VIVT
103 select CPU_COPY_V4WB if MMU
104 select CPU_TLB_V4WBI if MMU
106 The ARM920T is licensed to be produced by numerous vendors,
107 and is used in the Maverick EP9312 and the Samsung S3C2410.
109 More information on the Maverick EP9312 at
110 <http://linuxdevices.com/products/PD2382866068.html>.
112 Say Y if you want support for the ARM920T processor.
117 bool "Support ARM922T processor" if ARCH_INTEGRATOR
118 depends on ARCH_LH7A40X || ARCH_INTEGRATOR
119 default y if ARCH_LH7A40X
122 select CPU_CACHE_V4WT
123 select CPU_CACHE_VIVT
125 select CPU_COPY_V4WB if MMU
126 select CPU_TLB_V4WBI if MMU
128 The ARM922T is a version of the ARM920T, but with smaller
129 instruction and data caches. It is used in Altera's
130 Excalibur XA device family.
132 Say Y if you want support for the ARM922T processor.
137 bool "Support ARM925T processor" if ARCH_OMAP1
138 depends on ARCH_OMAP15XX
139 default y if ARCH_OMAP15XX
142 select CPU_CACHE_V4WT
143 select CPU_CACHE_VIVT
145 select CPU_COPY_V4WB if MMU
146 select CPU_TLB_V4WBI if MMU
148 The ARM925T is a mix between the ARM920T and ARM926T, but with
149 different instruction and data caches. It is used in TI's OMAP
152 Say Y if you want support for the ARM925T processor.
157 bool "Support ARM926T processor"
158 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
159 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
161 select CPU_ABRT_EV5TJ
162 select CPU_CACHE_VIVT
164 select CPU_COPY_V4WB if MMU
165 select CPU_TLB_V4WBI if MMU
167 This is a variant of the ARM920. It has slightly different
168 instruction sequences for cache and TLB operations. Curiously,
169 there is no documentation on it at the ARM corporate website.
171 Say Y if you want support for the ARM926T processor.
174 # ARM1020 - needs validating
176 bool "Support ARM1020T (rev 0) processor"
177 depends on ARCH_INTEGRATOR
180 select CPU_CACHE_V4WT
181 select CPU_CACHE_VIVT
183 select CPU_COPY_V4WB if MMU
184 select CPU_TLB_V4WBI if MMU
186 The ARM1020 is the 32K cached version of the ARM10 processor,
187 with an addition of a floating-point unit.
189 Say Y if you want support for the ARM1020 processor.
192 # ARM1020E - needs validating
194 bool "Support ARM1020E processor"
195 depends on ARCH_INTEGRATOR
198 select CPU_CACHE_V4WT
199 select CPU_CACHE_VIVT
201 select CPU_COPY_V4WB if MMU
202 select CPU_TLB_V4WBI if MMU
207 bool "Support ARM1022E processor"
208 depends on ARCH_INTEGRATOR
211 select CPU_CACHE_VIVT
213 select CPU_COPY_V4WB if MMU # can probably do better
214 select CPU_TLB_V4WBI if MMU
216 The ARM1022E is an implementation of the ARMv5TE architecture
217 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
218 embedded trace macrocell, and a floating-point unit.
220 Say Y if you want support for the ARM1022E processor.
225 bool "Support ARM1026EJ-S processor"
226 depends on ARCH_INTEGRATOR
228 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
229 select CPU_CACHE_VIVT
231 select CPU_COPY_V4WB if MMU # can probably do better
232 select CPU_TLB_V4WBI if MMU
234 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
235 based upon the ARM10 integer core.
237 Say Y if you want support for the ARM1026EJ-S processor.
242 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
243 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
244 select CPU_32v3 if ARCH_RPC
245 select CPU_32v4 if !ARCH_RPC
247 select CPU_CACHE_V4WB
248 select CPU_CACHE_VIVT
250 select CPU_COPY_V4WB if MMU
251 select CPU_TLB_V4WB if MMU
253 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
254 is available at five speeds ranging from 100 MHz to 233 MHz.
255 More information is available at
256 <http://developer.intel.com/design/strong/sa110.htm>.
258 Say Y if you want support for the SA-110 processor.
264 depends on ARCH_SA1100
268 select CPU_CACHE_V4WB
269 select CPU_CACHE_VIVT
271 select CPU_TLB_V4WB if MMU
276 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
280 select CPU_CACHE_VIVT
282 select CPU_TLB_V4WBI if MMU
284 # XScale Core Version 3
287 depends on ARCH_IXP23XX
291 select CPU_CACHE_VIVT
293 select CPU_TLB_V4WBI if MMU
298 bool "Support ARM V6 processor"
299 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
303 select CPU_CACHE_VIPT
305 select CPU_COPY_V6 if MMU
306 select CPU_TLB_V6 if MMU
310 bool "Support ARM V6K processor extensions" if !SMP
314 Say Y here if your ARMv6 processor supports the 'K' extension.
315 This enables the kernel to use some instructions not present
316 on previous processors, and as such a kernel build with this
317 enabled will not boot on processors with do not support these
320 # Figure out what processor architecture version we should be using.
321 # This defines the compiler instruction set which depends on the machine type.
324 select TLS_REG_EMUL if SMP || !MMU
325 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
329 select TLS_REG_EMUL if SMP || !MMU
330 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
334 select TLS_REG_EMUL if SMP || !MMU
335 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
339 select TLS_REG_EMUL if SMP || !MMU
340 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
358 config CPU_ABRT_EV5TJ
371 config CPU_CACHE_V4WT
374 config CPU_CACHE_V4WB
380 config CPU_CACHE_VIVT
383 config CPU_CACHE_VIPT
387 # The copy-page model
400 # This selects the TLB model
404 ARM Architecture Version 3 TLB.
409 ARM Architecture Version 4 TLB with writethrough cache.
414 ARM Architecture Version 4 TLB with writeback cache.
419 ARM Architecture Version 4 TLB with writeback cache and invalidate
420 instruction cache entry.
430 Processor has the CP15 register.
436 Processor has the CP15 register, which has MMU related registers.
442 Processor has the CP15 register, which has MPU related registers.
445 # CPU supports 36-bit I/O
450 comment "Processor Features"
453 bool "Support Thumb user binaries"
454 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
457 Say Y if you want to include kernel support for running user space
460 The Thumb instruction set is a compressed form of the standard ARM
461 instruction set resulting in smaller binaries at the expense of
462 slightly less efficient code.
464 If you don't know what this all is, saying Y is a safe choice.
466 config CPU_BIG_ENDIAN
467 bool "Build big-endian kernel"
468 depends on ARCH_SUPPORTS_BIG_ENDIAN
470 Say Y if you plan on running a kernel in big-endian mode.
471 Note that your board must be properly built and your board
472 port must properly enable any big-endian related features
473 of your chipset/board/processor.
475 config CPU_ICACHE_DISABLE
476 bool "Disable I-Cache (I-bit)"
477 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
479 Say Y here to disable the processor instruction cache. Unless
480 you have a reason not to or are unsure, say N.
482 config CPU_DCACHE_DISABLE
483 bool "Disable D-Cache (C-bit)"
486 Say Y here to disable the processor data cache. Unless
487 you have a reason not to or are unsure, say N.
489 config CPU_DCACHE_WRITETHROUGH
490 bool "Force write through D-cache"
491 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
492 default y if CPU_ARM925T
494 Say Y here to use the data cache in writethrough mode. Unless you
495 specifically require this or are unsure, say N.
497 config CPU_CACHE_ROUND_ROBIN
498 bool "Round robin I and D cache replacement algorithm"
499 depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
501 Say Y here to use the predictable round-robin cache replacement
502 policy. Unless you specifically require this or are unsure, say N.
504 config CPU_BPREDICT_DISABLE
505 bool "Disable branch prediction"
506 depends on CPU_ARM1020 || CPU_V6
508 Say Y here to disable branch prediction. If unsure, say N.
513 An SMP system using a pre-ARMv6 processor (there are apparently
514 a few prototypes like that in existence) and therefore access to
515 that required register must be emulated.
519 depends on !TLS_REG_EMUL
520 default y if SMP || CPU_32v7
522 This selects support for the CP15 thread register.
523 It is defined to be available on some ARMv6 processors (including
524 all SMP capable ARMv6's) or later processors. User space may
525 assume directly accessing that register and always obtain the
526 expected value only on ARMv7 and above.
528 config NEEDS_SYSCALL_FOR_CMPXCHG
531 SMP on a pre-ARMv6 processor? Well OK then.
532 Forget about fast user space cmpxchg support.
533 It is just not possible.