2 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * These are the low level assembler for performing cache and TLB
23 * functions on the arm1020.
25 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 #include <linux/linkage.h>
28 #include <linux/config.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/pgtable.h>
34 #include <asm/procinfo.h>
35 #include <asm/ptrace.h>
36 #include <asm/hardware.h>
39 * This is the maximum size of an area which will be invalidated
40 * using the single invalidate entry instructions. Anything larger
41 * than this, and we go for the whole cache.
43 * This value should be chosen such that we choose the cheapest
46 #define MAX_AREA_SIZE 32768
49 * The size of one data cache line.
51 #define CACHE_DLINESIZE 32
54 * The number of data cache segments.
56 #define CACHE_DSEGMENTS 16
59 * The number of lines in a cache segment.
61 #define CACHE_DENTRIES 64
64 * This is the size at which it becomes more efficient to
65 * clean the whole cache, rather than using the individual
66 * cache line maintainence instructions.
68 #define CACHE_DLIMIT 32768
72 * cpu_arm1020_proc_init()
74 ENTRY(cpu_arm1020_proc_init)
78 * cpu_arm1020_proc_fin()
80 ENTRY(cpu_arm1020_proc_fin)
82 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
84 bl arm1020_flush_kern_cache_all
85 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
86 bic r0, r0, #0x1000 @ ...i............
87 bic r0, r0, #0x000e @ ............wca.
88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
92 * cpu_arm1020_reset(loc)
94 * Perform a soft reset of the system. Put the CPU into the
95 * same state as it would be if it had been reset, and branch
96 * to what would be the reset vector.
98 * loc: location to jump to for soft reset
101 ENTRY(cpu_arm1020_reset)
103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
105 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
107 bic ip, ip, #0x000f @ ............wcam
108 bic ip, ip, #0x1100 @ ...i...s........
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
113 * cpu_arm1020_do_idle()
116 ENTRY(cpu_arm1020_do_idle)
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
120 /* ================================= CACHE ================================ */
124 * flush_user_cache_all()
126 * Invalidate all cache entries in a particular address
129 ENTRY(arm1020_flush_user_cache_all)
132 * flush_kern_cache_all()
134 * Clean and invalidate the entire cache.
136 ENTRY(arm1020_flush_kern_cache_all)
140 #ifndef CONFIG_CPU_DCACHE_DISABLE
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
142 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
143 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
146 subs r3, r3, #1 << 26
147 bcs 2b @ entries 63 to 0
149 bcs 1b @ segments 15 to 0
152 #ifndef CONFIG_CPU_ICACHE_DISABLE
153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
159 * flush_user_cache_range(start, end, flags)
161 * Invalidate a range of cache entries in the specified
164 * - start - start address (inclusive)
165 * - end - end address (exclusive)
166 * - flags - vm_flags for this space
168 ENTRY(arm1020_flush_user_cache_range)
170 sub r3, r1, r0 @ calculate total size
171 cmp r3, #CACHE_DLIMIT
172 bhs __flush_whole_cache
174 #ifndef CONFIG_CPU_DCACHE_DISABLE
175 mcr p15, 0, ip, c7, c10, 4
176 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
177 mcr p15, 0, ip, c7, c10, 4 @ drain WB
178 add r0, r0, #CACHE_DLINESIZE
183 #ifndef CONFIG_CPU_ICACHE_DISABLE
184 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
186 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
190 * coherent_kern_range(start, end)
192 * Ensure coherency between the Icache and the Dcache in the
193 * region described by start. If you have non-snooping
194 * Harvard caches, you need to implement this function.
196 * - start - virtual start address
197 * - end - virtual end address
199 ENTRY(arm1020_coherent_kern_range)
203 * coherent_user_range(start, end)
205 * Ensure coherency between the Icache and the Dcache in the
206 * region described by start. If you have non-snooping
207 * Harvard caches, you need to implement this function.
209 * - start - virtual start address
210 * - end - virtual end address
212 ENTRY(arm1020_coherent_user_range)
214 bic r0, r0, #CACHE_DLINESIZE - 1
215 mcr p15, 0, ip, c7, c10, 4
217 #ifndef CONFIG_CPU_DCACHE_DISABLE
218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
219 mcr p15, 0, ip, c7, c10, 4 @ drain WB
221 #ifndef CONFIG_CPU_ICACHE_DISABLE
222 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
224 add r0, r0, #CACHE_DLINESIZE
227 mcr p15, 0, ip, c7, c10, 4 @ drain WB
231 * flush_kern_dcache_page(void *page)
233 * Ensure no D cache aliasing occurs, either with itself or
236 * - page - page aligned address
238 ENTRY(arm1020_flush_kern_dcache_page)
240 #ifndef CONFIG_CPU_DCACHE_DISABLE
242 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
243 mcr p15, 0, ip, c7, c10, 4 @ drain WB
244 add r0, r0, #CACHE_DLINESIZE
248 mcr p15, 0, ip, c7, c10, 4 @ drain WB
252 * dma_inv_range(start, end)
254 * Invalidate (discard) the specified virtual address range.
255 * May not write back any entries. If 'start' or 'end'
256 * are not cache line aligned, those lines must be written
259 * - start - virtual start address
260 * - end - virtual end address
264 ENTRY(arm1020_dma_inv_range)
266 #ifndef CONFIG_CPU_DCACHE_DISABLE
267 tst r0, #CACHE_DLINESIZE - 1
268 bic r0, r0, #CACHE_DLINESIZE - 1
269 mcrne p15, 0, ip, c7, c10, 4
270 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
271 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
272 tst r1, #CACHE_DLINESIZE - 1
273 mcrne p15, 0, ip, c7, c10, 4
274 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
275 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
276 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
277 add r0, r0, #CACHE_DLINESIZE
281 mcr p15, 0, ip, c7, c10, 4 @ drain WB
285 * dma_clean_range(start, end)
287 * Clean the specified virtual address range.
289 * - start - virtual start address
290 * - end - virtual end address
294 ENTRY(arm1020_dma_clean_range)
296 #ifndef CONFIG_CPU_DCACHE_DISABLE
297 bic r0, r0, #CACHE_DLINESIZE - 1
298 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
299 mcr p15, 0, ip, c7, c10, 4 @ drain WB
300 add r0, r0, #CACHE_DLINESIZE
304 mcr p15, 0, ip, c7, c10, 4 @ drain WB
308 * dma_flush_range(start, end)
310 * Clean and invalidate the specified virtual address range.
312 * - start - virtual start address
313 * - end - virtual end address
315 ENTRY(arm1020_dma_flush_range)
317 #ifndef CONFIG_CPU_DCACHE_DISABLE
318 bic r0, r0, #CACHE_DLINESIZE - 1
319 mcr p15, 0, ip, c7, c10, 4
320 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
321 mcr p15, 0, ip, c7, c10, 4 @ drain WB
322 add r0, r0, #CACHE_DLINESIZE
326 mcr p15, 0, ip, c7, c10, 4 @ drain WB
329 ENTRY(arm1020_cache_fns)
330 .long arm1020_flush_kern_cache_all
331 .long arm1020_flush_user_cache_all
332 .long arm1020_flush_user_cache_range
333 .long arm1020_coherent_kern_range
334 .long arm1020_coherent_user_range
335 .long arm1020_flush_kern_dcache_page
336 .long arm1020_dma_inv_range
337 .long arm1020_dma_clean_range
338 .long arm1020_dma_flush_range
341 ENTRY(cpu_arm1020_dcache_clean_area)
342 #ifndef CONFIG_CPU_DCACHE_DISABLE
344 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
345 mcr p15, 0, ip, c7, c10, 4 @ drain WB
346 add r0, r0, #CACHE_DLINESIZE
347 subs r1, r1, #CACHE_DLINESIZE
352 /* =============================== PageTable ============================== */
355 * cpu_arm1020_switch_mm(pgd)
357 * Set the translation base pointer to be as described by pgd.
359 * pgd: new page tables
362 ENTRY(cpu_arm1020_switch_mm)
363 #ifndef CONFIG_CPU_DCACHE_DISABLE
364 mcr p15, 0, r3, c7, c10, 4
365 mov r1, #0xF @ 16 segments
366 1: mov r3, #0x3F @ 64 entries
367 2: mov ip, r3, LSL #26 @ shift up entry
368 orr ip, ip, r1, LSL #5 @ shift in/up index
369 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
371 mcr p15, 0, ip, c7, c10, 4
374 bge 2b @ entries 3F to 0
377 bge 1b @ segments 15 to 0
381 #ifndef CONFIG_CPU_ICACHE_DISABLE
382 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
384 mcr p15, 0, r1, c7, c10, 4 @ drain WB
385 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
386 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
390 * cpu_arm1020_set_pte(ptep, pte)
392 * Set a PTE and flush it out
395 ENTRY(cpu_arm1020_set_pte)
396 str r1, [r0], #-2048 @ linux version
398 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
400 bic r2, r1, #PTE_SMALL_AP_MASK
401 bic r2, r2, #PTE_TYPE_MASK
402 orr r2, r2, #PTE_TYPE_SMALL
404 tst r1, #L_PTE_USER @ User?
405 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
407 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
408 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
410 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
413 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
414 eor r3, r1, #0x0a @ C & small page?
418 str r2, [r0] @ hardware version
420 #ifndef CONFIG_CPU_DCACHE_DISABLE
421 mcr p15, 0, r0, c7, c10, 4
422 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
424 mcr p15, 0, r0, c7, c10, 4 @ drain WB
429 .type __arm1020_setup, #function
432 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
433 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
434 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
435 mrc p15, 0, r0, c1, c0 @ get control register v4
436 ldr r5, arm1020_cr1_clear
438 ldr r5, arm1020_cr1_set
440 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
441 orr r0, r0, #0x4000 @ .R.. .... .... ....
444 .size __arm1020_setup, . - __arm1020_setup
448 * .RVI ZFRS BLDP WCAM
449 * .011 1001 ..11 0101
451 .type arm1020_cr1_clear, #object
452 .type arm1020_cr1_set, #object
461 * Purpose : Function pointers used to access above functions - all calls
464 .type arm1020_processor_functions, #object
465 arm1020_processor_functions:
466 .word v4t_early_abort
467 .word cpu_arm1020_proc_init
468 .word cpu_arm1020_proc_fin
469 .word cpu_arm1020_reset
470 .word cpu_arm1020_do_idle
471 .word cpu_arm1020_dcache_clean_area
472 .word cpu_arm1020_switch_mm
473 .word cpu_arm1020_set_pte
474 .size arm1020_processor_functions, . - arm1020_processor_functions
478 .type cpu_arch_name, #object
481 .size cpu_arch_name, . - cpu_arch_name
483 .type cpu_elf_name, #object
486 .size cpu_elf_name, . - cpu_elf_name
488 .type cpu_arm1020_name, #object
491 #ifndef CONFIG_CPU_ICACHE_DISABLE
494 #ifndef CONFIG_CPU_DCACHE_DISABLE
496 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
502 #ifndef CONFIG_CPU_BPREDICT_DISABLE
505 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
509 .size cpu_arm1020_name, . - cpu_arm1020_name
513 .section ".proc.info.init", #alloc, #execinstr
515 .type __arm1020_proc_info,#object
517 .long 0x4104a200 @ ARM 1020T (Architecture v5T)
519 .long PMD_TYPE_SECT | \
520 PMD_SECT_AP_WRITE | \
525 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
526 .long cpu_arm1020_name
527 .long arm1020_processor_functions
530 .long arm1020_cache_fns
531 .size __arm1020_proc_info, . - __arm1020_proc_info