2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
29 #include <asm/system.h>
30 #include <asm/hardware.h>
34 #include <asm/arch/tc.h>
39 #define debug_printk(x) printk x
41 #define debug_printk(x)
44 #ifndef CONFIG_ARCH_OMAP1
45 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
46 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
49 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
52 #define OMAP_DMA_ACTIVE 0x01
53 #define OMAP_DMA_CCR_EN (1 << 7)
54 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
56 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
58 static int enable_1510_mode = 0;
66 void (* callback)(int lch, u16 ch_status, void *data);
69 #ifndef CONFIG_ARCH_OMAP1
70 /* required for Dynamic chaining */
81 #ifndef CONFIG_ARCH_OMAP1
82 struct dma_link_info {
84 int no_of_lchs_linked;
95 static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
97 /* Chain handling macros */
98 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
100 dma_linked_lch[chain_id].q_head = \
101 dma_linked_lch[chain_id].q_tail = \
102 dma_linked_lch[chain_id].q_count = 0; \
104 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
105 (dma_linked_lch[chain_id].no_of_lchs_linked == \
106 dma_linked_lch[chain_id].q_count)
107 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
109 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
110 dma_linked_lch[chain_id].q_count) \
112 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
113 (0 == dma_linked_lch[chain_id].q_count)
114 #define __OMAP_DMA_CHAIN_INCQ(end) \
115 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
116 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
119 dma_linked_lch[chain_id].q_count--; \
122 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
124 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
125 dma_linked_lch[chain_id].q_count++; \
128 static int dma_chan_count;
130 static spinlock_t dma_chan_lock;
131 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
133 static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
134 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
135 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
136 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
137 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
138 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
141 static inline void disable_lnk(int lch);
142 static void omap_disable_channel_irq(int lch);
143 static inline void omap_enable_channel_irq(int lch);
145 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
148 #ifdef CONFIG_ARCH_OMAP15XX
149 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
150 int omap_dma_in_1510_mode(void)
152 return enable_1510_mode;
155 #define omap_dma_in_1510_mode() 0
158 #ifdef CONFIG_ARCH_OMAP1
159 static inline int get_gdma_dev(int req)
161 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
162 int shift = ((req - 1) % 5) * 6;
164 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
167 static inline void set_gdma_dev(int req, int dev)
169 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
170 int shift = ((req - 1) % 5) * 6;
174 l &= ~(0x3f << shift);
175 l |= (dev - 1) << shift;
179 #define set_gdma_dev(req, dev) do {} while (0)
182 static void clear_lch_regs(int lch)
185 u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
187 for (i = 0; i < 0x2c; i += 2)
188 omap_writew(0, lch_base + i);
191 void omap_set_dma_priority(int lch, int dst_port, int priority)
196 if (cpu_class_is_omap1()) {
198 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
199 reg = OMAP_TC_OCPT1_PRIOR;
201 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
202 reg = OMAP_TC_OCPT2_PRIOR;
204 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
205 reg = OMAP_TC_EMIFF_PRIOR;
207 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
208 reg = OMAP_TC_EMIFS_PRIOR;
216 l |= (priority & 0xf) << 8;
220 if (cpu_class_is_omap2()) {
222 OMAP_DMA_CCR_REG(lch) |= (1 << 6);
224 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
228 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
229 int frame_count, int sync_mode,
230 int dma_trigger, int src_or_dst_synch)
232 OMAP_DMA_CSDP_REG(lch) &= ~0x03;
233 OMAP_DMA_CSDP_REG(lch) |= data_type;
235 if (cpu_class_is_omap1()) {
236 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
237 if (sync_mode == OMAP_DMA_SYNC_FRAME)
238 OMAP_DMA_CCR_REG(lch) |= 1 << 5;
240 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
241 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
242 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
245 if (cpu_class_is_omap2() && dma_trigger) {
246 u32 val = OMAP_DMA_CCR_REG(lch);
249 if (dma_trigger > 63)
251 if (dma_trigger > 31)
255 val |= (dma_trigger & 0x1f);
257 if (sync_mode & OMAP_DMA_SYNC_FRAME)
262 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
267 if (src_or_dst_synch)
268 val |= 1 << 24; /* source synch */
270 val &= ~(1 << 24); /* dest synch */
272 OMAP_DMA_CCR_REG(lch) = val;
275 OMAP_DMA_CEN_REG(lch) = elem_count;
276 OMAP_DMA_CFN_REG(lch) = frame_count;
279 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
283 BUG_ON(omap_dma_in_1510_mode());
285 if (cpu_class_is_omap2()) {
290 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
292 case OMAP_DMA_CONSTANT_FILL:
295 case OMAP_DMA_TRANSPARENT_COPY:
298 case OMAP_DMA_COLOR_DIS:
303 OMAP1_DMA_CCR2_REG(lch) = w;
305 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
306 /* Default is channel type 2D */
308 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
309 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
310 w |= 1; /* Channel type G */
312 OMAP1_DMA_LCH_CTRL_REG(lch) = w;
315 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
317 if (cpu_class_is_omap2()) {
318 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
319 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
323 /* Note that src_port is only for omap1 */
324 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
325 unsigned long src_start,
326 int src_ei, int src_fi)
328 if (cpu_class_is_omap1()) {
329 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
330 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
333 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
334 OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
336 if (cpu_class_is_omap1()) {
337 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
338 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
341 if (cpu_class_is_omap2())
342 OMAP2_DMA_CSSA_REG(lch) = src_start;
344 OMAP_DMA_CSEI_REG(lch) = src_ei;
345 OMAP_DMA_CSFI_REG(lch) = src_fi;
348 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
350 omap_set_dma_transfer_params(lch, params->data_type,
351 params->elem_count, params->frame_count,
352 params->sync_mode, params->trigger,
353 params->src_or_dst_synch);
354 omap_set_dma_src_params(lch, params->src_port,
355 params->src_amode, params->src_start,
356 params->src_ei, params->src_fi);
358 omap_set_dma_dest_params(lch, params->dst_port,
359 params->dst_amode, params->dst_start,
360 params->dst_ei, params->dst_fi);
361 if (params->read_prio || params->write_prio)
362 omap_dma_set_prio_lch(lch, params->read_prio,
366 void omap_set_dma_src_index(int lch, int eidx, int fidx)
368 if (cpu_class_is_omap2()) {
372 OMAP_DMA_CSEI_REG(lch) = eidx;
373 OMAP_DMA_CSFI_REG(lch) = fidx;
376 void omap_set_dma_src_data_pack(int lch, int enable)
378 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
380 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
383 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
385 unsigned int burst = 0;
386 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
388 switch (burst_mode) {
389 case OMAP_DMA_DATA_BURST_DIS:
391 case OMAP_DMA_DATA_BURST_4:
392 if (cpu_class_is_omap2())
397 case OMAP_DMA_DATA_BURST_8:
398 if (cpu_class_is_omap2()) {
402 /* not supported by current hardware on OMAP1
406 case OMAP_DMA_DATA_BURST_16:
407 if (cpu_class_is_omap2()) {
411 /* OMAP1 don't support burst 16
417 OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
420 /* Note that dest_port is only for OMAP1 */
421 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
422 unsigned long dest_start,
423 int dst_ei, int dst_fi)
425 if (cpu_class_is_omap1()) {
426 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
427 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
430 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
431 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
433 if (cpu_class_is_omap1()) {
434 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
435 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
438 if (cpu_class_is_omap2())
439 OMAP2_DMA_CDSA_REG(lch) = dest_start;
441 OMAP_DMA_CDEI_REG(lch) = dst_ei;
442 OMAP_DMA_CDFI_REG(lch) = dst_fi;
445 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
447 if (cpu_class_is_omap2()) {
451 OMAP_DMA_CDEI_REG(lch) = eidx;
452 OMAP_DMA_CDFI_REG(lch) = fidx;
455 void omap_set_dma_dest_data_pack(int lch, int enable)
457 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
459 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
462 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
464 unsigned int burst = 0;
465 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
467 switch (burst_mode) {
468 case OMAP_DMA_DATA_BURST_DIS:
470 case OMAP_DMA_DATA_BURST_4:
471 if (cpu_class_is_omap2())
476 case OMAP_DMA_DATA_BURST_8:
477 if (cpu_class_is_omap2())
482 case OMAP_DMA_DATA_BURST_16:
483 if (cpu_class_is_omap2()) {
487 /* OMAP1 don't support burst 16
491 printk(KERN_ERR "Invalid DMA burst mode\n");
495 OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
498 static inline void omap_enable_channel_irq(int lch)
503 if (cpu_class_is_omap1())
504 status = OMAP_DMA_CSR_REG(lch);
505 else if (cpu_class_is_omap2())
506 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
508 /* Enable some nice interrupts. */
509 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
511 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
514 static void omap_disable_channel_irq(int lch)
516 if (cpu_class_is_omap2())
517 OMAP_DMA_CICR_REG(lch) = 0;
520 void omap_enable_dma_irq(int lch, u16 bits)
522 dma_chan[lch].enabled_irqs |= bits;
525 void omap_disable_dma_irq(int lch, u16 bits)
527 dma_chan[lch].enabled_irqs &= ~bits;
530 static inline void enable_lnk(int lch)
532 if (cpu_class_is_omap1())
533 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
535 /* Set the ENABLE_LNK bits */
536 if (dma_chan[lch].next_lch != -1)
537 OMAP_DMA_CLNK_CTRL_REG(lch) =
538 dma_chan[lch].next_lch | (1 << 15);
540 #ifndef CONFIG_ARCH_OMAP1
541 if (dma_chan[lch].next_linked_ch != -1)
542 OMAP_DMA_CLNK_CTRL_REG(lch) =
543 dma_chan[lch].next_linked_ch | (1 << 15);
547 static inline void disable_lnk(int lch)
549 /* Disable interrupts */
550 if (cpu_class_is_omap1()) {
551 OMAP_DMA_CICR_REG(lch) = 0;
552 /* Set the STOP_LNK bit */
553 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
556 if (cpu_class_is_omap2()) {
557 omap_disable_channel_irq(lch);
558 /* Clear the ENABLE_LNK bit */
559 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
562 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
565 static inline void omap2_enable_irq_lch(int lch)
569 if (!cpu_class_is_omap2())
572 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
574 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
577 int omap_request_dma(int dev_id, const char *dev_name,
578 void (* callback)(int lch, u16 ch_status, void *data),
579 void *data, int *dma_ch_out)
581 int ch, free_ch = -1;
583 struct omap_dma_lch *chan;
585 spin_lock_irqsave(&dma_chan_lock, flags);
586 for (ch = 0; ch < dma_chan_count; ch++) {
587 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
594 spin_unlock_irqrestore(&dma_chan_lock, flags);
597 chan = dma_chan + free_ch;
598 chan->dev_id = dev_id;
600 if (cpu_class_is_omap1())
601 clear_lch_regs(free_ch);
603 if (cpu_class_is_omap2())
604 omap_clear_dma(free_ch);
606 spin_unlock_irqrestore(&dma_chan_lock, flags);
608 chan->dev_name = dev_name;
609 chan->callback = callback;
611 #ifndef CONFIG_ARCH_OMAP1
614 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
616 if (cpu_class_is_omap1())
617 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
618 else if (cpu_class_is_omap2())
619 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
620 OMAP2_DMA_TRANS_ERR_IRQ;
622 if (cpu_is_omap16xx()) {
623 /* If the sync device is set, configure it dynamically. */
625 set_gdma_dev(free_ch + 1, dev_id);
626 dev_id = free_ch + 1;
628 /* Disable the 1510 compatibility mode and set the sync device
630 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
631 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
632 OMAP_DMA_CCR_REG(free_ch) = dev_id;
635 if (cpu_class_is_omap2()) {
636 omap2_enable_irq_lch(free_ch);
638 omap_enable_channel_irq(free_ch);
639 /* Clear the CSR register and IRQ status register */
640 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
641 omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0);
644 *dma_ch_out = free_ch;
649 void omap_free_dma(int lch)
653 spin_lock_irqsave(&dma_chan_lock, flags);
654 if (dma_chan[lch].dev_id == -1) {
655 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
657 spin_unlock_irqrestore(&dma_chan_lock, flags);
660 dma_chan[lch].dev_id = -1;
661 dma_chan[lch].next_lch = -1;
662 dma_chan[lch].callback = NULL;
663 spin_unlock_irqrestore(&dma_chan_lock, flags);
665 if (cpu_class_is_omap1()) {
666 /* Disable all DMA interrupts for the channel. */
667 OMAP_DMA_CICR_REG(lch) = 0;
668 /* Make sure the DMA transfer is stopped. */
669 OMAP_DMA_CCR_REG(lch) = 0;
672 if (cpu_class_is_omap2()) {
674 /* Disable interrupts */
675 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
677 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
679 /* Clear the CSR register and IRQ status register */
680 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
681 omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0);
683 /* Disable all DMA interrupts for the channel. */
684 OMAP_DMA_CICR_REG(lch) = 0;
686 /* Make sure the DMA transfer is stopped. */
687 OMAP_DMA_CCR_REG(lch) = 0;
693 * @brief omap_dma_set_global_params : Set global priority settings for dma
696 * @param max_fifo_depth
697 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
698 * DMA_THREAD_RESERVE_ONET
699 * DMA_THREAD_RESERVE_TWOT
700 * DMA_THREAD_RESERVE_THREET
703 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
707 if (!cpu_class_is_omap2()) {
708 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __FUNCTION__);
715 reg = (arb_rate & 0xff) << 16;
716 reg |= (0xff & max_fifo_depth);
718 omap_writel(reg, OMAP_DMA4_GCR_REG);
720 EXPORT_SYMBOL(omap_dma_set_global_params);
723 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
726 * @param read_prio - Read priority
727 * @param write_prio - Write priority
728 * Both of the above can be set with one of the following values :
729 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
732 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
733 unsigned char write_prio)
737 if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) {
738 printk(KERN_ERR "Invalid channel id\n");
741 w = OMAP_DMA_CCR_REG(lch);
742 w &= ~((1 << 6) | (1 << 26));
743 if (cpu_is_omap2430() || cpu_is_omap34xx())
744 w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
746 w |= ((read_prio & 0x1) << 6);
748 OMAP_DMA_CCR_REG(lch) = w;
751 EXPORT_SYMBOL(omap_dma_set_prio_lch);
754 * Clears any DMA state so the DMA engine is ready to restart with new buffers
755 * through omap_start_dma(). Any buffers in flight are discarded.
757 void omap_clear_dma(int lch)
761 local_irq_save(flags);
763 if (cpu_class_is_omap1()) {
765 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
767 /* Clear pending interrupts */
768 status = OMAP_DMA_CSR_REG(lch);
771 if (cpu_class_is_omap2()) {
773 u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
774 for (i = 0; i < 0x44; i += 4)
775 omap_writel(0, lch_base + i);
778 local_irq_restore(flags);
781 void omap_start_dma(int lch)
783 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
784 int next_lch, cur_lch;
785 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
787 dma_chan_link_map[lch] = 1;
788 /* Set the link register of the first channel */
791 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
792 cur_lch = dma_chan[lch].next_lch;
794 next_lch = dma_chan[cur_lch].next_lch;
796 /* The loop case: we've been here already */
797 if (dma_chan_link_map[cur_lch])
799 /* Mark the current channel */
800 dma_chan_link_map[cur_lch] = 1;
803 omap_enable_channel_irq(cur_lch);
806 } while (next_lch != -1);
807 } else if (cpu_class_is_omap2()) {
808 /* Errata: Need to write lch even if not using chaining */
809 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
812 omap_enable_channel_irq(lch);
814 /* Errata: On ES2.0 BUFFERING disable must be set.
815 * This will always fail on ES1.0 */
816 if (cpu_is_omap24xx()) {
817 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
820 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
822 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
825 void omap_stop_dma(int lch)
827 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
828 int next_lch, cur_lch = lch;
829 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
831 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
833 /* The loop case: we've been here already */
834 if (dma_chan_link_map[cur_lch])
836 /* Mark the current channel */
837 dma_chan_link_map[cur_lch] = 1;
839 disable_lnk(cur_lch);
841 next_lch = dma_chan[cur_lch].next_lch;
843 } while (next_lch != -1);
848 /* Disable all interrupts on the channel */
849 if (cpu_class_is_omap1())
850 OMAP_DMA_CICR_REG(lch) = 0;
852 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
853 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
857 * Allows changing the DMA callback function or data. This may be needed if
858 * the driver shares a single DMA channel for multiple dma triggers.
860 int omap_set_dma_callback(int lch,
861 void (* callback)(int lch, u16 ch_status, void *data),
869 spin_lock_irqsave(&dma_chan_lock, flags);
870 if (dma_chan[lch].dev_id == -1) {
871 printk(KERN_ERR "DMA callback for not set for free channel\n");
872 spin_unlock_irqrestore(&dma_chan_lock, flags);
875 dma_chan[lch].callback = callback;
876 dma_chan[lch].data = data;
877 spin_unlock_irqrestore(&dma_chan_lock, flags);
883 * Returns current physical source address for the given DMA channel.
884 * If the channel is running the caller must disable interrupts prior calling
885 * this function and process the returned value before re-enabling interrupt to
886 * prevent races with the interrupt handler. Note that in continuous mode there
887 * is a chance for CSSA_L register overflow inbetween the two reads resulting
888 * in incorrect return value.
890 dma_addr_t omap_get_dma_src_pos(int lch)
892 dma_addr_t offset = 0;
894 if (cpu_class_is_omap1())
895 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
896 (OMAP1_DMA_CSSA_U_REG(lch) << 16));
898 if (cpu_class_is_omap2())
899 offset = OMAP_DMA_CSAC_REG(lch);
905 * Returns current physical destination address for the given DMA channel.
906 * If the channel is running the caller must disable interrupts prior calling
907 * this function and process the returned value before re-enabling interrupt to
908 * prevent races with the interrupt handler. Note that in continuous mode there
909 * is a chance for CDSA_L register overflow inbetween the two reads resulting
910 * in incorrect return value.
912 dma_addr_t omap_get_dma_dst_pos(int lch)
914 dma_addr_t offset = 0;
916 if (cpu_class_is_omap1())
917 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
918 (OMAP1_DMA_CDSA_U_REG(lch) << 16));
920 if (cpu_class_is_omap2())
921 offset = OMAP_DMA_CDAC_REG(lch);
927 * Returns current source transfer counting for the given DMA channel.
928 * Can be used to monitor the progress of a transfer inside a block.
929 * It must be called with disabled interrupts.
931 int omap_get_dma_src_addr_counter(int lch)
933 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
936 int omap_dma_running(void)
940 /* Check if LCD DMA is running */
941 if (cpu_is_omap16xx())
942 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
945 for (lch = 0; lch < dma_chan_count; lch++)
946 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
953 * lch_queue DMA will start right after lch_head one is finished.
954 * For this DMA link to start, you still need to start (see omap_start_dma)
955 * the first one. That will fire up the entire queue.
957 void omap_dma_link_lch (int lch_head, int lch_queue)
959 if (omap_dma_in_1510_mode()) {
960 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
965 if ((dma_chan[lch_head].dev_id == -1) ||
966 (dma_chan[lch_queue].dev_id == -1)) {
967 printk(KERN_ERR "omap_dma: trying to link "
968 "non requested channels\n");
972 dma_chan[lch_head].next_lch = lch_queue;
976 * Once the DMA queue is stopped, we can destroy it.
978 void omap_dma_unlink_lch (int lch_head, int lch_queue)
980 if (omap_dma_in_1510_mode()) {
981 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
986 if (dma_chan[lch_head].next_lch != lch_queue ||
987 dma_chan[lch_head].next_lch == -1) {
988 printk(KERN_ERR "omap_dma: trying to unlink "
989 "non linked channels\n");
994 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
995 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
996 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
997 "before unlinking\n");
1001 dma_chan[lch_head].next_lch = -1;
1004 #ifndef CONFIG_ARCH_OMAP1
1005 /* Create chain of DMA channesls */
1006 static void create_dma_lch_chain(int lch_head, int lch_queue)
1010 /* Check if this is the first link in chain */
1011 if (dma_chan[lch_head].next_linked_ch == -1) {
1012 dma_chan[lch_head].next_linked_ch = lch_queue;
1013 dma_chan[lch_head].prev_linked_ch = lch_queue;
1014 dma_chan[lch_queue].next_linked_ch = lch_head;
1015 dma_chan[lch_queue].prev_linked_ch = lch_head;
1018 /* a link exists, link the new channel in circular chain */
1020 dma_chan[lch_queue].next_linked_ch =
1021 dma_chan[lch_head].next_linked_ch;
1022 dma_chan[lch_queue].prev_linked_ch = lch_head;
1023 dma_chan[lch_head].next_linked_ch = lch_queue;
1024 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1028 w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
1031 OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
1033 w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
1035 w |= (dma_chan[lch_queue].next_linked_ch);
1036 OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
1040 * @brief omap_request_dma_chain : Request a chain of DMA channels
1042 * @param dev_id - Device id using the dma channel
1043 * @param dev_name - Device name
1044 * @param callback - Call back function
1046 * @no_of_chans - Number of channels requested
1047 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1048 * OMAP_DMA_DYNAMIC_CHAIN
1049 * @params - Channel parameters
1051 * @return - Succes : 0
1052 * Failure: -EINVAL/-ENOMEM
1054 int omap_request_dma_chain(int dev_id, const char *dev_name,
1055 void (*callback) (int chain_id, u16 ch_status,
1057 int *chain_id, int no_of_chans, int chain_mode,
1058 struct omap_dma_channel_params params)
1063 /* Is the chain mode valid ? */
1064 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1065 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1066 printk(KERN_ERR "Invalid chain mode requested \n");
1070 if (unlikely((no_of_chans < 1
1071 || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) {
1072 printk(KERN_ERR "Invalid Number of channels requested\n");
1076 /* Allocate a queue to maintain the status of the channels
1078 channels = (int *)kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1079 if (channels == NULL) {
1080 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1084 /* request and reserve DMA channels for the chain */
1085 for (i = 0; i < no_of_chans; i++) {
1086 err = omap_request_dma(dev_id, dev_name,
1087 callback, 0, &channels[i]);
1090 for (j = 0; j < i; j++)
1091 omap_free_dma(channels[j]);
1093 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1096 dma_chan[channels[i]].next_linked_ch = -1;
1097 dma_chan[channels[i]].prev_linked_ch = -1;
1098 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1101 * Allowing client drivers to set common parameters now,
1102 * so that later only relevant (src_start, dest_start
1103 * and element count) can be set
1105 omap_set_dma_params(channels[i], ¶ms);
1108 *chain_id = channels[0];
1109 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1110 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1111 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1112 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1114 for (i = 0; i < no_of_chans; i++)
1115 dma_chan[channels[i]].chain_id = *chain_id;
1117 /* Reset the Queue pointers */
1118 OMAP_DMA_CHAIN_QINIT(*chain_id);
1120 /* Set up the chain */
1121 if (no_of_chans == 1)
1122 create_dma_lch_chain(channels[0], channels[0]);
1124 for (i = 0; i < (no_of_chans - 1); i++)
1125 create_dma_lch_chain(channels[i], channels[i + 1]);
1129 EXPORT_SYMBOL(omap_request_dma_chain);
1132 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1133 * params after setting it. Dont do this while dma is running!!
1135 * @param chain_id - Chained logical channel id.
1138 * @return - Success : 0
1141 int omap_modify_dma_chain_params(int chain_id,
1142 struct omap_dma_channel_params params)
1147 /* Check for input params */
1148 if (unlikely((chain_id < 0
1149 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1150 printk(KERN_ERR "Invalid chain id\n");
1154 /* Check if the chain exists */
1155 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1156 printk(KERN_ERR "Chain doesn't exists\n");
1159 channels = dma_linked_lch[chain_id].linked_dmach_q;
1161 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1163 * Allowing client drivers to set common parameters now,
1164 * so that later only relevant (src_start, dest_start
1165 * and element count) can be set
1167 omap_set_dma_params(channels[i], ¶ms);
1171 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1174 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1178 * @return - Success : 0
1181 int omap_free_dma_chain(int chain_id)
1186 /* Check for input params */
1187 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1188 printk(KERN_ERR "Invalid chain id\n");
1192 /* Check if the chain exists */
1193 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1194 printk(KERN_ERR "Chain doesn't exists\n");
1198 channels = dma_linked_lch[chain_id].linked_dmach_q;
1199 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1200 dma_chan[channels[i]].next_linked_ch = -1;
1201 dma_chan[channels[i]].prev_linked_ch = -1;
1202 dma_chan[channels[i]].chain_id = -1;
1203 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1204 omap_free_dma(channels[i]);
1209 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1210 dma_linked_lch[chain_id].chain_mode = -1;
1211 dma_linked_lch[chain_id].chain_state = -1;
1214 EXPORT_SYMBOL(omap_free_dma_chain);
1217 * @brief omap_dma_chain_status - Check if the chain is in
1218 * active / inactive state.
1221 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1224 int omap_dma_chain_status(int chain_id)
1226 /* Check for input params */
1227 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1228 printk(KERN_ERR "Invalid chain id\n");
1232 /* Check if the chain exists */
1233 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1234 printk(KERN_ERR "Chain doesn't exists\n");
1237 debug_printk((KERN_INFO "CHAINID=%d, qcnt=%d\n", chain_id,
1238 dma_linked_lch[chain_id].q_count));
1240 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1241 return OMAP_DMA_CHAIN_INACTIVE;
1242 return OMAP_DMA_CHAIN_ACTIVE;
1244 EXPORT_SYMBOL(omap_dma_chain_status);
1247 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1248 * set the params and start the transfer.
1251 * @param src_start - buffer start address
1252 * @param dest_start - Dest address
1254 * @param frame_count
1255 * @param callbk_data - channel callback parameter data.
1257 * @return - Success : start_dma status
1258 * Failure: -EINVAL/-EBUSY
1260 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1261 int elem_count, int frame_count, void *callbk_data)
1267 /* if buffer size is less than 1 then there is
1268 * no use of starting the chain */
1269 if (elem_count < 1) {
1270 printk(KERN_ERR "Invalid buffer size\n");
1274 /* Check for input params */
1275 if (unlikely((chain_id < 0
1276 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1277 printk(KERN_ERR "Invalid chain id\n");
1281 /* Check if the chain exists */
1282 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1283 printk(KERN_ERR "Chain doesn't exist\n");
1287 /* Check if all the channels in chain are in use */
1288 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1291 /* Frame count may be negative in case of indexed transfers */
1292 channels = dma_linked_lch[chain_id].linked_dmach_q;
1294 /* Get a free channel */
1295 lch = channels[dma_linked_lch[chain_id].q_tail];
1297 /* Store the callback data */
1298 dma_chan[lch].data = callbk_data;
1300 /* Increment the q_tail */
1301 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1303 /* Set the params to the free channel */
1305 OMAP2_DMA_CSSA_REG(lch) = src_start;
1306 if (dest_start != 0)
1307 OMAP2_DMA_CDSA_REG(lch) = dest_start;
1309 /* Write the buffer size */
1310 OMAP_DMA_CEN_REG(lch) = elem_count;
1311 OMAP_DMA_CFN_REG(lch) = frame_count;
1313 /* If the chain is dynamically linked,
1314 * then we may have to start the chain if its not active */
1315 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1317 /* In Dynamic chain, if the chain is not started,
1318 * queue the channel */
1319 if (dma_linked_lch[chain_id].chain_state ==
1320 DMA_CHAIN_NOTSTARTED) {
1321 /* Enable the link in previous channel */
1322 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1324 enable_lnk(dma_chan[lch].prev_linked_ch);
1325 dma_chan[lch].state = DMA_CH_QUEUED;
1328 /* Chain is already started, make sure its active,
1329 * if not then start the chain */
1333 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1335 enable_lnk(dma_chan[lch].prev_linked_ch);
1336 dma_chan[lch].state = DMA_CH_QUEUED;
1338 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
1339 (dma_chan[lch].prev_linked_ch)))) {
1340 disable_lnk(dma_chan[lch].
1342 debug_printk((KERN_INFO
1343 "\n prev ch is stopped\n"));
1348 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1350 enable_lnk(dma_chan[lch].prev_linked_ch);
1351 dma_chan[lch].state = DMA_CH_QUEUED;
1354 omap_enable_channel_irq(lch);
1356 w = OMAP_DMA_CCR_REG(lch);
1358 if ((0 == (w & (1 << 24))))
1362 if (start_dma == 1) {
1363 if (0 == (w & (1 << 7))) {
1365 dma_chan[lch].state = DMA_CH_STARTED;
1366 debug_printk((KERN_INFO
1367 "starting %d\n", lch));
1368 OMAP_DMA_CCR_REG(lch) = w;
1372 if (0 == (w & (1 << 7)))
1373 OMAP_DMA_CCR_REG(lch) = w;
1375 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1380 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1383 * @brief omap_start_dma_chain_transfers - Start the chain
1387 * @return - Success : 0
1388 * Failure : -EINVAL/-EBUSY
1390 int omap_start_dma_chain_transfers(int chain_id)
1395 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1396 printk(KERN_ERR "Invalid chain id\n");
1400 channels = dma_linked_lch[chain_id].linked_dmach_q;
1402 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1403 printk(KERN_ERR "Chain is already started \n");
1407 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1408 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1410 enable_lnk(channels[i]);
1411 omap_enable_channel_irq(channels[i]);
1414 omap_enable_channel_irq(channels[0]);
1417 w = OMAP_DMA_CCR_REG(channels[0]);
1419 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1420 dma_chan[channels[0]].state = DMA_CH_STARTED;
1422 if ((0 == (w & (1 << 24))))
1426 OMAP_DMA_CCR_REG(channels[0]) = w;
1428 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1431 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1434 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1438 * @return - Success : 0
1441 int omap_stop_dma_chain_transfers(int chain_id)
1447 /* Check for input params */
1448 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1449 printk(KERN_ERR "Invalid chain id\n");
1453 /* Check if the chain exists */
1454 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1455 printk(KERN_ERR "Chain doesn't exists\n");
1458 channels = dma_linked_lch[chain_id].linked_dmach_q;
1461 * Special programming model needed to disable DMA before end of block
1463 sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG);
1465 /* Middle mode reg set no Standby */
1466 w &= ~((1 << 12)|(1 << 13));
1467 omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG);
1469 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1471 /* Stop the Channel transmission */
1472 w = OMAP_DMA_CCR_REG(channels[i]);
1474 OMAP_DMA_CCR_REG(channels[i]) = w;
1476 /* Disable the link in all the channels */
1477 disable_lnk(channels[i]);
1478 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1481 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1483 /* Reset the Queue pointers */
1484 OMAP_DMA_CHAIN_QINIT(chain_id);
1486 /* Errata - put in the old value */
1487 omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG);
1490 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1492 /* Get the index of the ongoing DMA in chain */
1494 * @brief omap_get_dma_chain_index - Get the element and frame index
1495 * of the ongoing DMA in chain
1498 * @param ei - Element index
1499 * @param fi - Frame index
1501 * @return - Success : 0
1504 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1509 /* Check for input params */
1510 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1511 printk(KERN_ERR "Invalid chain id\n");
1515 /* Check if the chain exists */
1516 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1517 printk(KERN_ERR "Chain doesn't exists\n");
1523 channels = dma_linked_lch[chain_id].linked_dmach_q;
1525 /* Get the current channel */
1526 lch = channels[dma_linked_lch[chain_id].q_head];
1528 *ei = OMAP2_DMA_CCEN_REG(lch);
1529 *fi = OMAP2_DMA_CCFN_REG(lch);
1533 EXPORT_SYMBOL(omap_get_dma_chain_index);
1536 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1537 * ongoing DMA in chain
1541 * @return - Success : Destination position
1544 int omap_get_dma_chain_dst_pos(int chain_id)
1549 /* Check for input params */
1550 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1551 printk(KERN_ERR "Invalid chain id\n");
1555 /* Check if the chain exists */
1556 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1557 printk(KERN_ERR "Chain doesn't exists\n");
1561 channels = dma_linked_lch[chain_id].linked_dmach_q;
1563 /* Get the current channel */
1564 lch = channels[dma_linked_lch[chain_id].q_head];
1566 return (OMAP_DMA_CDAC_REG(lch));
1568 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1571 * @brief omap_get_dma_chain_src_pos - Get the source position
1572 * of the ongoing DMA in chain
1575 * @return - Success : Destination position
1578 int omap_get_dma_chain_src_pos(int chain_id)
1583 /* Check for input params */
1584 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
1585 printk(KERN_ERR "Invalid chain id\n");
1589 /* Check if the chain exists */
1590 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1591 printk(KERN_ERR "Chain doesn't exists\n");
1595 channels = dma_linked_lch[chain_id].linked_dmach_q;
1597 /* Get the current channel */
1598 lch = channels[dma_linked_lch[chain_id].q_head];
1600 return (OMAP_DMA_CSAC_REG(lch));
1602 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1605 /*----------------------------------------------------------------------------*/
1607 #ifdef CONFIG_ARCH_OMAP1
1609 static int omap1_dma_handle_ch(int ch)
1613 if (enable_1510_mode && ch >= 6) {
1614 csr = dma_chan[ch].saved_csr;
1615 dma_chan[ch].saved_csr = 0;
1617 csr = OMAP_DMA_CSR_REG(ch);
1618 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1619 dma_chan[ch + 6].saved_csr = csr >> 7;
1622 if ((csr & 0x3f) == 0)
1624 if (unlikely(dma_chan[ch].dev_id == -1)) {
1625 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1626 "%d (CSR %04x)\n", ch, csr);
1629 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1630 printk(KERN_WARNING "DMA timeout with device %d\n",
1631 dma_chan[ch].dev_id);
1632 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1633 printk(KERN_WARNING "DMA synchronization event drop occurred "
1634 "with device %d\n", dma_chan[ch].dev_id);
1635 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1636 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1637 if (likely(dma_chan[ch].callback != NULL))
1638 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1642 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1644 int ch = ((int) dev_id) - 1;
1648 int handled_now = 0;
1650 handled_now += omap1_dma_handle_ch(ch);
1651 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1652 handled_now += omap1_dma_handle_ch(ch + 6);
1655 handled += handled_now;
1658 return handled ? IRQ_HANDLED : IRQ_NONE;
1662 #define omap1_dma_irq_handler NULL
1665 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1667 static int omap2_dma_handle_ch(int ch)
1669 u32 status = OMAP_DMA_CSR_REG(ch);
1672 if (printk_ratelimit())
1673 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
1676 if (unlikely(dma_chan[ch].dev_id == -1)) {
1677 if (printk_ratelimit())
1678 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1679 "channel %d\n", status, ch);
1682 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1684 "DMA synchronization event drop occurred with device "
1685 "%d\n", dma_chan[ch].dev_id);
1686 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
1687 printk(KERN_INFO "DMA transaction error with device %d\n",
1688 dma_chan[ch].dev_id);
1689 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1690 printk(KERN_INFO "DMA secure error with device %d\n",
1691 dma_chan[ch].dev_id);
1692 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1693 printk(KERN_INFO "DMA misaligned error with device %d\n",
1694 dma_chan[ch].dev_id);
1696 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
1697 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
1699 /* If the ch is not chained then chain_id will be -1 */
1700 if (dma_chan[ch].chain_id != -1) {
1701 int chain_id = dma_chan[ch].chain_id;
1702 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1703 if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15))
1704 dma_chan[dma_chan[ch].next_linked_ch].state =
1706 if (dma_linked_lch[chain_id].chain_mode ==
1707 OMAP_DMA_DYNAMIC_CHAIN)
1710 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1711 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1713 status = OMAP_DMA_CSR_REG(ch);
1716 if (likely(dma_chan[ch].callback != NULL)) {
1717 if (dma_chan[ch].chain_id != -1)
1718 dma_chan[ch].callback(dma_chan[ch].chain_id, status,
1721 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1725 OMAP_DMA_CSR_REG(ch) = status;
1730 /* STATUS register count is from 1-32 while our is 0-31 */
1731 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1736 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
1738 if (printk_ratelimit())
1739 printk(KERN_WARNING "Spurious DMA IRQ\n");
1742 for (i = 0; i < OMAP_LOGICAL_DMA_CH_COUNT && val != 0; i++) {
1744 omap2_dma_handle_ch(i);
1751 static struct irqaction omap24xx_dma_irq = {
1753 .handler = omap2_dma_irq_handler,
1754 .flags = IRQF_DISABLED
1758 static struct irqaction omap24xx_dma_irq;
1761 /*----------------------------------------------------------------------------*/
1763 static struct lcd_dma_info {
1766 void (* callback)(u16 status, void *data);
1770 unsigned long addr, size;
1771 int rotate, data_type, xres, yres;
1777 int single_transfer;
1780 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1783 lcd_dma.addr = addr;
1784 lcd_dma.data_type = data_type;
1785 lcd_dma.xres = fb_xres;
1786 lcd_dma.yres = fb_yres;
1789 void omap_set_lcd_dma_src_port(int port)
1791 lcd_dma.src_port = port;
1794 void omap_set_lcd_dma_ext_controller(int external)
1796 lcd_dma.ext_ctrl = external;
1799 void omap_set_lcd_dma_single_transfer(int single)
1801 lcd_dma.single_transfer = single;
1805 void omap_set_lcd_dma_b1_rotation(int rotate)
1807 if (omap_dma_in_1510_mode()) {
1808 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1812 lcd_dma.rotate = rotate;
1815 void omap_set_lcd_dma_b1_mirror(int mirror)
1817 if (omap_dma_in_1510_mode()) {
1818 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1821 lcd_dma.mirror = mirror;
1824 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1826 if (omap_dma_in_1510_mode()) {
1827 printk(KERN_ERR "DMA virtual resulotion is not supported "
1831 lcd_dma.vxres = vxres;
1834 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1836 if (omap_dma_in_1510_mode()) {
1837 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
1840 lcd_dma.xscale = xscale;
1841 lcd_dma.yscale = yscale;
1844 static void set_b1_regs(void)
1846 unsigned long top, bottom;
1849 unsigned long en, fn;
1851 unsigned long vxres;
1852 unsigned int xscale, yscale;
1854 switch (lcd_dma.data_type) {
1855 case OMAP_DMA_DATA_TYPE_S8:
1858 case OMAP_DMA_DATA_TYPE_S16:
1861 case OMAP_DMA_DATA_TYPE_S32:
1869 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1870 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1871 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1872 BUG_ON(vxres < lcd_dma.xres);
1873 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1874 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1875 switch (lcd_dma.rotate) {
1877 if (!lcd_dma.mirror) {
1878 top = PIXADDR(0, 0);
1879 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1880 /* 1510 DMA requires the bottom address to be 2 more
1881 * than the actual last memory access location. */
1882 if (omap_dma_in_1510_mode() &&
1883 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1885 ei = PIXSTEP(0, 0, 1, 0);
1886 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1888 top = PIXADDR(lcd_dma.xres - 1, 0);
1889 bottom = PIXADDR(0, lcd_dma.yres - 1);
1890 ei = PIXSTEP(1, 0, 0, 0);
1891 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1897 if (!lcd_dma.mirror) {
1898 top = PIXADDR(0, lcd_dma.yres - 1);
1899 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1900 ei = PIXSTEP(0, 1, 0, 0);
1901 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1903 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1904 bottom = PIXADDR(0, 0);
1905 ei = PIXSTEP(0, 1, 0, 0);
1906 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1912 if (!lcd_dma.mirror) {
1913 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1914 bottom = PIXADDR(0, 0);
1915 ei = PIXSTEP(1, 0, 0, 0);
1916 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1918 top = PIXADDR(0, lcd_dma.yres - 1);
1919 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1920 ei = PIXSTEP(0, 0, 1, 0);
1921 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1927 if (!lcd_dma.mirror) {
1928 top = PIXADDR(lcd_dma.xres - 1, 0);
1929 bottom = PIXADDR(0, lcd_dma.yres - 1);
1930 ei = PIXSTEP(0, 0, 0, 1);
1931 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1933 top = PIXADDR(0, 0);
1934 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1935 ei = PIXSTEP(0, 0, 0, 1);
1936 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1943 return; /* Suppress warning about uninitialized vars */
1946 if (omap_dma_in_1510_mode()) {
1947 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1948 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1949 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1950 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1956 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1957 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1958 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1959 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1961 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1962 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1964 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1966 w |= lcd_dma.data_type;
1967 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1969 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1970 /* Always set the source port as SDRAM for now*/
1972 if (lcd_dma.callback != NULL)
1973 w |= 1 << 1; /* Block interrupt enable */
1976 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1978 if (!(lcd_dma.rotate || lcd_dma.mirror ||
1979 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1982 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1983 /* Set the double-indexed addressing mode */
1985 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1987 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1988 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1989 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1992 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
1996 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1997 if (unlikely(!(w & (1 << 3)))) {
1998 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2003 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2005 if (lcd_dma.callback != NULL)
2006 lcd_dma.callback(w, lcd_dma.cb_data);
2011 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
2014 spin_lock_irq(&lcd_dma.lock);
2015 if (lcd_dma.reserved) {
2016 spin_unlock_irq(&lcd_dma.lock);
2017 printk(KERN_ERR "LCD DMA channel already reserved\n");
2021 lcd_dma.reserved = 1;
2022 spin_unlock_irq(&lcd_dma.lock);
2023 lcd_dma.callback = callback;
2024 lcd_dma.cb_data = data;
2026 lcd_dma.single_transfer = 0;
2032 lcd_dma.ext_ctrl = 0;
2033 lcd_dma.src_port = 0;
2038 void omap_free_lcd_dma(void)
2040 spin_lock(&lcd_dma.lock);
2041 if (!lcd_dma.reserved) {
2042 spin_unlock(&lcd_dma.lock);
2043 printk(KERN_ERR "LCD DMA is not reserved\n");
2047 if (!enable_1510_mode)
2048 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2049 OMAP1610_DMA_LCD_CCR);
2050 lcd_dma.reserved = 0;
2051 spin_unlock(&lcd_dma.lock);
2054 void omap_enable_lcd_dma(void)
2058 /* Set the Enable bit only if an external controller is
2059 * connected. Otherwise the OMAP internal controller will
2060 * start the transfer when it gets enabled.
2062 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2065 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2067 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2071 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2073 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2076 void omap_setup_lcd_dma(void)
2078 BUG_ON(lcd_dma.active);
2079 if (!enable_1510_mode) {
2080 /* Set some reasonable defaults */
2081 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2082 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2083 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2086 if (!enable_1510_mode) {
2089 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2090 /* If DMA was already active set the end_prog bit to have
2091 * the programmed register set loaded into the active
2094 w |= 1 << 11; /* End_prog */
2095 if (!lcd_dma.single_transfer)
2096 w |= (3 << 8); /* Auto_init, repeat */
2097 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2101 void omap_stop_lcd_dma(void)
2106 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2109 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2111 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2113 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2115 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2118 /*----------------------------------------------------------------------------*/
2120 static int __init omap_init_dma(void)
2124 if (cpu_is_omap15xx()) {
2125 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2127 enable_1510_mode = 1;
2128 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2129 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2130 omap_readw(OMAP_DMA_HW_ID));
2131 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2132 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
2133 omap_readw(OMAP_DMA_CAPS_0_L),
2134 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
2135 omap_readw(OMAP_DMA_CAPS_1_L),
2136 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
2137 omap_readw(OMAP_DMA_CAPS_4));
2138 if (!enable_1510_mode) {
2141 /* Disable OMAP 3.0/3.1 compatibility mode. */
2142 w = omap_readw(OMAP_DMA_GSCR);
2144 omap_writew(w, OMAP_DMA_GSCR);
2145 dma_chan_count = 16;
2148 if (cpu_is_omap16xx()) {
2151 /* this would prevent OMAP sleep */
2152 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2154 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2156 } else if (cpu_class_is_omap2()) {
2157 u8 revision = omap_readb(OMAP_DMA4_REVISION);
2158 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2159 revision >> 4, revision & 0xf);
2160 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
2166 memset(&lcd_dma, 0, sizeof(lcd_dma));
2167 spin_lock_init(&lcd_dma.lock);
2168 spin_lock_init(&dma_chan_lock);
2169 memset(&dma_chan, 0, sizeof(dma_chan));
2171 for (ch = 0; ch < dma_chan_count; ch++) {
2173 dma_chan[ch].dev_id = -1;
2174 dma_chan[ch].next_lch = -1;
2176 if (ch >= 6 && enable_1510_mode)
2179 if (cpu_class_is_omap1()) {
2180 /* request_irq() doesn't like dev_id (ie. ch) being
2181 * zero, so we have to kludge around this. */
2182 r = request_irq(omap1_dma_irq[ch],
2183 omap1_dma_irq_handler, 0, "DMA",
2188 printk(KERN_ERR "unable to request IRQ %d "
2189 "for DMA (error %d)\n",
2190 omap1_dma_irq[ch], r);
2191 for (i = 0; i < ch; i++)
2192 free_irq(omap1_dma_irq[i],
2199 if (cpu_is_omap2430() || cpu_is_omap34xx())
2200 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2201 DMA_DEFAULT_FIFO_DEPTH, 0);
2203 if (cpu_class_is_omap2())
2204 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2206 /* FIXME: Update LCD DMA to work on 24xx */
2207 if (cpu_class_is_omap1()) {
2208 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2213 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2215 for (i = 0; i < dma_chan_count; i++)
2216 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2224 arch_initcall(omap_init_dma);
2226 EXPORT_SYMBOL(omap_get_dma_src_pos);
2227 EXPORT_SYMBOL(omap_get_dma_dst_pos);
2228 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
2229 EXPORT_SYMBOL(omap_clear_dma);
2230 EXPORT_SYMBOL(omap_set_dma_priority);
2231 EXPORT_SYMBOL(omap_request_dma);
2232 EXPORT_SYMBOL(omap_free_dma);
2233 EXPORT_SYMBOL(omap_start_dma);
2234 EXPORT_SYMBOL(omap_stop_dma);
2235 EXPORT_SYMBOL(omap_set_dma_callback);
2236 EXPORT_SYMBOL(omap_enable_dma_irq);
2237 EXPORT_SYMBOL(omap_disable_dma_irq);
2239 EXPORT_SYMBOL(omap_set_dma_transfer_params);
2240 EXPORT_SYMBOL(omap_set_dma_color_mode);
2241 EXPORT_SYMBOL(omap_set_dma_write_mode);
2243 EXPORT_SYMBOL(omap_set_dma_src_params);
2244 EXPORT_SYMBOL(omap_set_dma_src_index);
2245 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
2246 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
2248 EXPORT_SYMBOL(omap_set_dma_dest_params);
2249 EXPORT_SYMBOL(omap_set_dma_dest_index);
2250 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
2251 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
2253 EXPORT_SYMBOL(omap_set_dma_params);
2255 EXPORT_SYMBOL(omap_dma_link_lch);
2256 EXPORT_SYMBOL(omap_dma_unlink_lch);
2258 EXPORT_SYMBOL(omap_request_lcd_dma);
2259 EXPORT_SYMBOL(omap_free_lcd_dma);
2260 EXPORT_SYMBOL(omap_enable_lcd_dma);
2261 EXPORT_SYMBOL(omap_setup_lcd_dma);
2262 EXPORT_SYMBOL(omap_stop_lcd_dma);
2263 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2264 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2265 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2266 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2267 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2268 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2269 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);