2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/ptrace.h>
18 #include <linux/sysdev.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <asm/hardware.h>
24 #include <asm/arch/irqs.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/mach/irq.h>
31 * OMAP1510 GPIO registers
33 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
34 #define OMAP1510_GPIO_DATA_INPUT 0x00
35 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
36 #define OMAP1510_GPIO_DIR_CONTROL 0x08
37 #define OMAP1510_GPIO_INT_CONTROL 0x0c
38 #define OMAP1510_GPIO_INT_MASK 0x10
39 #define OMAP1510_GPIO_INT_STATUS 0x14
40 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42 #define OMAP1510_IH_GPIO_BASE 64
45 * OMAP1610 specific GPIO registers
47 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
48 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
49 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
50 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
51 #define OMAP1610_GPIO_REVISION 0x0000
52 #define OMAP1610_GPIO_SYSCONFIG 0x0010
53 #define OMAP1610_GPIO_SYSSTATUS 0x0014
54 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
55 #define OMAP1610_GPIO_IRQENABLE1 0x001c
56 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
57 #define OMAP1610_GPIO_DATAIN 0x002c
58 #define OMAP1610_GPIO_DATAOUT 0x0030
59 #define OMAP1610_GPIO_DIRECTION 0x0034
60 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
61 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
62 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
63 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
64 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
65 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
66 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
67 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70 * OMAP730 specific GPIO registers
72 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
73 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
74 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
75 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
76 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
77 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
78 #define OMAP730_GPIO_DATA_INPUT 0x00
79 #define OMAP730_GPIO_DATA_OUTPUT 0x04
80 #define OMAP730_GPIO_DIR_CONTROL 0x08
81 #define OMAP730_GPIO_INT_CONTROL 0x0c
82 #define OMAP730_GPIO_INT_MASK 0x10
83 #define OMAP730_GPIO_INT_STATUS 0x14
86 * omap24xx specific GPIO registers
88 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
89 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
90 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
91 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
93 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
94 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
95 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
96 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
97 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
99 #define OMAP24XX_GPIO_REVISION 0x0000
100 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
101 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
102 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
103 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
104 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
105 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
106 #define OMAP24XX_GPIO_CTRL 0x0030
107 #define OMAP24XX_GPIO_OE 0x0034
108 #define OMAP24XX_GPIO_DATAIN 0x0038
109 #define OMAP24XX_GPIO_DATAOUT 0x003c
110 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
111 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
112 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
113 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
114 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
115 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
116 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
117 #define OMAP24XX_GPIO_SETWKUENA 0x0084
118 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
119 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
124 u16 virtual_irq_start;
127 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
131 #ifdef CONFIG_ARCH_OMAP24XX
132 u32 non_wakeup_gpios;
133 u32 enabled_non_wakeup_gpios;
136 u32 saved_fallingdetect;
137 u32 saved_risingdetect;
142 #define METHOD_MPUIO 0
143 #define METHOD_GPIO_1510 1
144 #define METHOD_GPIO_1610 2
145 #define METHOD_GPIO_730 3
146 #define METHOD_GPIO_24XX 4
148 #ifdef CONFIG_ARCH_OMAP16XX
149 static struct gpio_bank gpio_bank_1610[5] = {
150 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
151 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
152 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
153 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
154 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
158 #ifdef CONFIG_ARCH_OMAP15XX
159 static struct gpio_bank gpio_bank_1510[2] = {
160 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
161 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
165 #ifdef CONFIG_ARCH_OMAP730
166 static struct gpio_bank gpio_bank_730[7] = {
167 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
168 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
169 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
170 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
171 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
172 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
173 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
177 #ifdef CONFIG_ARCH_OMAP24XX
179 static struct gpio_bank gpio_bank_242x[4] = {
180 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
181 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
182 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
183 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
186 static struct gpio_bank gpio_bank_243x[5] = {
187 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
188 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
189 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
190 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
191 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
196 static struct gpio_bank *gpio_bank;
197 static int gpio_bank_count;
199 static inline struct gpio_bank *get_gpio_bank(int gpio)
201 #ifdef CONFIG_ARCH_OMAP15XX
202 if (cpu_is_omap15xx()) {
203 if (OMAP_GPIO_IS_MPUIO(gpio))
204 return &gpio_bank[0];
205 return &gpio_bank[1];
208 #if defined(CONFIG_ARCH_OMAP16XX)
209 if (cpu_is_omap16xx()) {
210 if (OMAP_GPIO_IS_MPUIO(gpio))
211 return &gpio_bank[0];
212 return &gpio_bank[1 + (gpio >> 4)];
215 #ifdef CONFIG_ARCH_OMAP730
216 if (cpu_is_omap730()) {
217 if (OMAP_GPIO_IS_MPUIO(gpio))
218 return &gpio_bank[0];
219 return &gpio_bank[1 + (gpio >> 5)];
222 #ifdef CONFIG_ARCH_OMAP24XX
223 if (cpu_is_omap24xx())
224 return &gpio_bank[gpio >> 5];
228 static inline int get_gpio_index(int gpio)
230 #ifdef CONFIG_ARCH_OMAP730
231 if (cpu_is_omap730())
234 #ifdef CONFIG_ARCH_OMAP24XX
235 if (cpu_is_omap24xx())
241 static inline int gpio_valid(int gpio)
245 #ifndef CONFIG_ARCH_OMAP24XX
246 if (OMAP_GPIO_IS_MPUIO(gpio)) {
247 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
252 #ifdef CONFIG_ARCH_OMAP15XX
253 if (cpu_is_omap15xx() && gpio < 16)
256 #if defined(CONFIG_ARCH_OMAP16XX)
257 if ((cpu_is_omap16xx()) && gpio < 64)
260 #ifdef CONFIG_ARCH_OMAP730
261 if (cpu_is_omap730() && gpio < 192)
264 #ifdef CONFIG_ARCH_OMAP24XX
265 if (cpu_is_omap24xx() && gpio < 128)
271 static int check_gpio(int gpio)
273 if (unlikely(gpio_valid(gpio)) < 0) {
274 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
281 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
283 void __iomem *reg = bank->base;
286 switch (bank->method) {
287 #ifdef CONFIG_ARCH_OMAP1
289 reg += OMAP_MPUIO_IO_CNTL;
292 #ifdef CONFIG_ARCH_OMAP15XX
293 case METHOD_GPIO_1510:
294 reg += OMAP1510_GPIO_DIR_CONTROL;
297 #ifdef CONFIG_ARCH_OMAP16XX
298 case METHOD_GPIO_1610:
299 reg += OMAP1610_GPIO_DIRECTION;
302 #ifdef CONFIG_ARCH_OMAP730
303 case METHOD_GPIO_730:
304 reg += OMAP730_GPIO_DIR_CONTROL;
307 #ifdef CONFIG_ARCH_OMAP24XX
308 case METHOD_GPIO_24XX:
309 reg += OMAP24XX_GPIO_OE;
316 l = __raw_readl(reg);
321 __raw_writel(l, reg);
324 void omap_set_gpio_direction(int gpio, int is_input)
326 struct gpio_bank *bank;
328 if (check_gpio(gpio) < 0)
330 bank = get_gpio_bank(gpio);
331 spin_lock(&bank->lock);
332 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
333 spin_unlock(&bank->lock);
336 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
338 void __iomem *reg = bank->base;
341 switch (bank->method) {
342 #ifdef CONFIG_ARCH_OMAP1
344 reg += OMAP_MPUIO_OUTPUT;
345 l = __raw_readl(reg);
352 #ifdef CONFIG_ARCH_OMAP15XX
353 case METHOD_GPIO_1510:
354 reg += OMAP1510_GPIO_DATA_OUTPUT;
355 l = __raw_readl(reg);
362 #ifdef CONFIG_ARCH_OMAP16XX
363 case METHOD_GPIO_1610:
365 reg += OMAP1610_GPIO_SET_DATAOUT;
367 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
371 #ifdef CONFIG_ARCH_OMAP730
372 case METHOD_GPIO_730:
373 reg += OMAP730_GPIO_DATA_OUTPUT;
374 l = __raw_readl(reg);
381 #ifdef CONFIG_ARCH_OMAP24XX
382 case METHOD_GPIO_24XX:
384 reg += OMAP24XX_GPIO_SETDATAOUT;
386 reg += OMAP24XX_GPIO_CLEARDATAOUT;
394 __raw_writel(l, reg);
397 void omap_set_gpio_dataout(int gpio, int enable)
399 struct gpio_bank *bank;
401 if (check_gpio(gpio) < 0)
403 bank = get_gpio_bank(gpio);
404 spin_lock(&bank->lock);
405 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
406 spin_unlock(&bank->lock);
409 int omap_get_gpio_datain(int gpio)
411 struct gpio_bank *bank;
414 if (check_gpio(gpio) < 0)
416 bank = get_gpio_bank(gpio);
418 switch (bank->method) {
419 #ifdef CONFIG_ARCH_OMAP1
421 reg += OMAP_MPUIO_INPUT_LATCH;
424 #ifdef CONFIG_ARCH_OMAP15XX
425 case METHOD_GPIO_1510:
426 reg += OMAP1510_GPIO_DATA_INPUT;
429 #ifdef CONFIG_ARCH_OMAP16XX
430 case METHOD_GPIO_1610:
431 reg += OMAP1610_GPIO_DATAIN;
434 #ifdef CONFIG_ARCH_OMAP730
435 case METHOD_GPIO_730:
436 reg += OMAP730_GPIO_DATA_INPUT;
439 #ifdef CONFIG_ARCH_OMAP24XX
440 case METHOD_GPIO_24XX:
441 reg += OMAP24XX_GPIO_DATAIN;
447 return (__raw_readl(reg)
448 & (1 << get_gpio_index(gpio))) != 0;
451 #define MOD_REG_BIT(reg, bit_mask, set) \
453 int l = __raw_readl(base + reg); \
454 if (set) l |= bit_mask; \
455 else l &= ~bit_mask; \
456 __raw_writel(l, base + reg); \
459 #ifdef CONFIG_ARCH_OMAP24XX
460 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
462 void __iomem *base = bank->base;
463 u32 gpio_bit = 1 << gpio;
465 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
466 trigger & __IRQT_LOWLVL);
467 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
468 trigger & __IRQT_HIGHLVL);
469 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
470 trigger & __IRQT_RISEDGE);
471 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
472 trigger & __IRQT_FALEDGE);
473 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
475 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
477 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
480 bank->enabled_non_wakeup_gpios |= gpio_bit;
482 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
484 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
485 * triggering requested. */
489 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
491 void __iomem *reg = bank->base;
494 switch (bank->method) {
495 #ifdef CONFIG_ARCH_OMAP1
497 reg += OMAP_MPUIO_GPIO_INT_EDGE;
498 l = __raw_readl(reg);
499 if (trigger & __IRQT_RISEDGE)
501 else if (trigger & __IRQT_FALEDGE)
507 #ifdef CONFIG_ARCH_OMAP15XX
508 case METHOD_GPIO_1510:
509 reg += OMAP1510_GPIO_INT_CONTROL;
510 l = __raw_readl(reg);
511 if (trigger & __IRQT_RISEDGE)
513 else if (trigger & __IRQT_FALEDGE)
519 #ifdef CONFIG_ARCH_OMAP16XX
520 case METHOD_GPIO_1610:
522 reg += OMAP1610_GPIO_EDGE_CTRL2;
524 reg += OMAP1610_GPIO_EDGE_CTRL1;
526 l = __raw_readl(reg);
527 l &= ~(3 << (gpio << 1));
528 if (trigger & __IRQT_RISEDGE)
529 l |= 2 << (gpio << 1);
530 if (trigger & __IRQT_FALEDGE)
531 l |= 1 << (gpio << 1);
533 /* Enable wake-up during idle for dynamic tick */
534 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
536 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
539 #ifdef CONFIG_ARCH_OMAP730
540 case METHOD_GPIO_730:
541 reg += OMAP730_GPIO_INT_CONTROL;
542 l = __raw_readl(reg);
543 if (trigger & __IRQT_RISEDGE)
545 else if (trigger & __IRQT_FALEDGE)
551 #ifdef CONFIG_ARCH_OMAP24XX
552 case METHOD_GPIO_24XX:
553 set_24xx_gpio_triggering(bank, gpio, trigger);
559 __raw_writel(l, reg);
565 static int gpio_irq_type(unsigned irq, unsigned type)
567 struct gpio_bank *bank;
571 if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE)
572 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
574 gpio = irq - IH_GPIO_BASE;
576 if (check_gpio(gpio) < 0)
579 if (type & ~IRQ_TYPE_SENSE_MASK)
582 /* OMAP1 allows only only edge triggering */
583 if (!cpu_is_omap24xx()
584 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
587 bank = get_gpio_bank(gpio);
588 spin_lock(&bank->lock);
589 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
591 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
592 irq_desc[irq].status |= type;
594 spin_unlock(&bank->lock);
598 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
600 void __iomem *reg = bank->base;
602 switch (bank->method) {
603 #ifdef CONFIG_ARCH_OMAP1
605 /* MPUIO irqstatus is reset by reading the status register,
606 * so do nothing here */
609 #ifdef CONFIG_ARCH_OMAP15XX
610 case METHOD_GPIO_1510:
611 reg += OMAP1510_GPIO_INT_STATUS;
614 #ifdef CONFIG_ARCH_OMAP16XX
615 case METHOD_GPIO_1610:
616 reg += OMAP1610_GPIO_IRQSTATUS1;
619 #ifdef CONFIG_ARCH_OMAP730
620 case METHOD_GPIO_730:
621 reg += OMAP730_GPIO_INT_STATUS;
624 #ifdef CONFIG_ARCH_OMAP24XX
625 case METHOD_GPIO_24XX:
626 reg += OMAP24XX_GPIO_IRQSTATUS1;
633 __raw_writel(gpio_mask, reg);
635 /* Workaround for clearing DSP GPIO interrupts to allow retention */
636 if (cpu_is_omap2420())
637 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
640 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
642 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
645 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
647 void __iomem *reg = bank->base;
652 switch (bank->method) {
653 #ifdef CONFIG_ARCH_OMAP1
655 reg += OMAP_MPUIO_GPIO_MASKIT;
660 #ifdef CONFIG_ARCH_OMAP15XX
661 case METHOD_GPIO_1510:
662 reg += OMAP1510_GPIO_INT_MASK;
667 #ifdef CONFIG_ARCH_OMAP16XX
668 case METHOD_GPIO_1610:
669 reg += OMAP1610_GPIO_IRQENABLE1;
673 #ifdef CONFIG_ARCH_OMAP730
674 case METHOD_GPIO_730:
675 reg += OMAP730_GPIO_INT_MASK;
680 #ifdef CONFIG_ARCH_OMAP24XX
681 case METHOD_GPIO_24XX:
682 reg += OMAP24XX_GPIO_IRQENABLE1;
691 l = __raw_readl(reg);
698 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
700 void __iomem *reg = bank->base;
703 switch (bank->method) {
704 #ifdef CONFIG_ARCH_OMAP1
706 reg += OMAP_MPUIO_GPIO_MASKIT;
707 l = __raw_readl(reg);
714 #ifdef CONFIG_ARCH_OMAP15XX
715 case METHOD_GPIO_1510:
716 reg += OMAP1510_GPIO_INT_MASK;
717 l = __raw_readl(reg);
724 #ifdef CONFIG_ARCH_OMAP16XX
725 case METHOD_GPIO_1610:
727 reg += OMAP1610_GPIO_SET_IRQENABLE1;
729 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
733 #ifdef CONFIG_ARCH_OMAP730
734 case METHOD_GPIO_730:
735 reg += OMAP730_GPIO_INT_MASK;
736 l = __raw_readl(reg);
743 #ifdef CONFIG_ARCH_OMAP24XX
744 case METHOD_GPIO_24XX:
746 reg += OMAP24XX_GPIO_SETIRQENABLE1;
748 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
756 __raw_writel(l, reg);
759 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
761 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
765 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
766 * 1510 does not seem to have a wake-up register. If JTAG is connected
767 * to the target, system will wake up always on GPIO events. While
768 * system is running all registered GPIO interrupts need to have wake-up
769 * enabled. When system is suspended, only selected GPIO interrupts need
770 * to have wake-up enabled.
772 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
774 switch (bank->method) {
775 #ifdef CONFIG_ARCH_OMAP16XX
776 case METHOD_GPIO_1610:
777 spin_lock(&bank->lock);
779 bank->suspend_wakeup |= (1 << gpio);
781 bank->suspend_wakeup &= ~(1 << gpio);
782 spin_unlock(&bank->lock);
785 #ifdef CONFIG_ARCH_OMAP24XX
786 case METHOD_GPIO_24XX:
787 spin_lock(&bank->lock);
789 if (bank->non_wakeup_gpios & (1 << gpio)) {
790 printk(KERN_ERR "Unable to enable wakeup on "
791 "non-wakeup GPIO%d\n",
792 (bank - gpio_bank) * 32 + gpio);
793 spin_unlock(&bank->lock);
796 bank->suspend_wakeup |= (1 << gpio);
798 bank->suspend_wakeup &= ~(1 << gpio);
799 spin_unlock(&bank->lock);
803 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
809 static void _reset_gpio(struct gpio_bank *bank, int gpio)
811 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
812 _set_gpio_irqenable(bank, gpio, 0);
813 _clear_gpio_irqstatus(bank, gpio);
814 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
817 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
818 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
820 unsigned int gpio = irq - IH_GPIO_BASE;
821 struct gpio_bank *bank;
824 if (check_gpio(gpio) < 0)
826 bank = get_gpio_bank(gpio);
827 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
832 int omap_request_gpio(int gpio)
834 struct gpio_bank *bank;
836 if (check_gpio(gpio) < 0)
839 bank = get_gpio_bank(gpio);
840 spin_lock(&bank->lock);
841 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
842 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
844 spin_unlock(&bank->lock);
847 bank->reserved_map |= (1 << get_gpio_index(gpio));
849 /* Set trigger to none. You need to enable the desired trigger with
850 * request_irq() or set_irq_type().
852 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
854 #ifdef CONFIG_ARCH_OMAP15XX
855 if (bank->method == METHOD_GPIO_1510) {
858 /* Claim the pin for MPU */
859 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
860 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
863 spin_unlock(&bank->lock);
868 void omap_free_gpio(int gpio)
870 struct gpio_bank *bank;
872 if (check_gpio(gpio) < 0)
874 bank = get_gpio_bank(gpio);
875 spin_lock(&bank->lock);
876 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
877 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
879 spin_unlock(&bank->lock);
882 #ifdef CONFIG_ARCH_OMAP16XX
883 if (bank->method == METHOD_GPIO_1610) {
884 /* Disable wake-up during idle for dynamic tick */
885 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
886 __raw_writel(1 << get_gpio_index(gpio), reg);
889 #ifdef CONFIG_ARCH_OMAP24XX
890 if (bank->method == METHOD_GPIO_24XX) {
891 /* Disable wake-up during idle for dynamic tick */
892 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
893 __raw_writel(1 << get_gpio_index(gpio), reg);
896 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
897 _reset_gpio(bank, gpio);
898 spin_unlock(&bank->lock);
902 * We need to unmask the GPIO bank interrupt as soon as possible to
903 * avoid missing GPIO interrupts for other lines in the bank.
904 * Then we need to mask-read-clear-unmask the triggered GPIO lines
905 * in the bank to avoid missing nested interrupts for a GPIO line.
906 * If we wait to unmask individual GPIO lines in the bank after the
907 * line's interrupt handler has been run, we may miss some nested
910 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
912 void __iomem *isr_reg = NULL;
914 unsigned int gpio_irq;
915 struct gpio_bank *bank;
919 desc->chip->ack(irq);
921 bank = get_irq_data(irq);
922 #ifdef CONFIG_ARCH_OMAP1
923 if (bank->method == METHOD_MPUIO)
924 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
926 #ifdef CONFIG_ARCH_OMAP15XX
927 if (bank->method == METHOD_GPIO_1510)
928 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
930 #if defined(CONFIG_ARCH_OMAP16XX)
931 if (bank->method == METHOD_GPIO_1610)
932 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
934 #ifdef CONFIG_ARCH_OMAP730
935 if (bank->method == METHOD_GPIO_730)
936 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
938 #ifdef CONFIG_ARCH_OMAP24XX
939 if (bank->method == METHOD_GPIO_24XX)
940 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
943 u32 isr_saved, level_mask = 0;
946 enabled = _get_gpio_irqbank_mask(bank);
947 isr_saved = isr = __raw_readl(isr_reg) & enabled;
949 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
952 if (cpu_is_omap24xx()) {
954 __raw_readl(bank->base +
955 OMAP24XX_GPIO_LEVELDETECT0) |
956 __raw_readl(bank->base +
957 OMAP24XX_GPIO_LEVELDETECT1);
958 level_mask &= enabled;
961 /* clear edge sensitive interrupts before handler(s) are
962 called so that we don't miss any interrupt occurred while
964 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
965 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
966 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
968 /* if there is only edge sensitive GPIO pin interrupts
969 configured, we could unmask GPIO bank interrupt immediately */
970 if (!level_mask && !unmasked) {
972 desc->chip->unmask(irq);
980 gpio_irq = bank->virtual_irq_start;
981 for (; isr != 0; isr >>= 1, gpio_irq++) {
986 d = irq_desc + gpio_irq;
987 /* Don't run the handler if it's already running
988 * or was disabled lazely.
990 if (unlikely((d->depth ||
991 (d->status & IRQ_INPROGRESS)))) {
993 (gpio_irq - bank->virtual_irq_start);
994 /* The unmasking will be done by
995 * enable_irq in case it is disabled or
996 * after returning from the handler if
997 * it's already running.
999 _enable_gpio_irqbank(bank, irq_mask, 0);
1001 /* Level triggered interrupts
1002 * won't ever be reentered
1004 BUG_ON(level_mask & irq_mask);
1005 d->status |= IRQ_PENDING;
1010 desc_handle_irq(gpio_irq, d);
1012 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1014 (gpio_irq - bank->virtual_irq_start);
1015 d->status &= ~IRQ_PENDING;
1016 _enable_gpio_irqbank(bank, irq_mask, 1);
1017 retrigger |= irq_mask;
1021 if (cpu_is_omap24xx()) {
1022 /* clear level sensitive interrupts after handler(s) */
1023 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1024 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1025 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1029 /* if bank has any level sensitive GPIO pin interrupt
1030 configured, we must unmask the bank interrupt only after
1031 handler(s) are executed in order to avoid spurious bank
1034 desc->chip->unmask(irq);
1038 static void gpio_irq_shutdown(unsigned int irq)
1040 unsigned int gpio = irq - IH_GPIO_BASE;
1041 struct gpio_bank *bank = get_gpio_bank(gpio);
1043 _reset_gpio(bank, gpio);
1046 static void gpio_ack_irq(unsigned int irq)
1048 unsigned int gpio = irq - IH_GPIO_BASE;
1049 struct gpio_bank *bank = get_gpio_bank(gpio);
1051 _clear_gpio_irqstatus(bank, gpio);
1054 static void gpio_mask_irq(unsigned int irq)
1056 unsigned int gpio = irq - IH_GPIO_BASE;
1057 struct gpio_bank *bank = get_gpio_bank(gpio);
1059 _set_gpio_irqenable(bank, gpio, 0);
1062 static void gpio_unmask_irq(unsigned int irq)
1064 unsigned int gpio = irq - IH_GPIO_BASE;
1065 unsigned int gpio_idx = get_gpio_index(gpio);
1066 struct gpio_bank *bank = get_gpio_bank(gpio);
1068 _set_gpio_irqenable(bank, gpio_idx, 1);
1071 static struct irq_chip gpio_irq_chip = {
1073 .shutdown = gpio_irq_shutdown,
1074 .ack = gpio_ack_irq,
1075 .mask = gpio_mask_irq,
1076 .unmask = gpio_unmask_irq,
1077 .set_type = gpio_irq_type,
1078 .set_wake = gpio_wake_enable,
1081 /*---------------------------------------------------------------------*/
1083 #ifdef CONFIG_ARCH_OMAP1
1085 /* MPUIO uses the always-on 32k clock */
1087 static void mpuio_ack_irq(unsigned int irq)
1089 /* The ISR is reset automatically, so do nothing here. */
1092 static void mpuio_mask_irq(unsigned int irq)
1094 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1095 struct gpio_bank *bank = get_gpio_bank(gpio);
1097 _set_gpio_irqenable(bank, gpio, 0);
1100 static void mpuio_unmask_irq(unsigned int irq)
1102 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1103 struct gpio_bank *bank = get_gpio_bank(gpio);
1105 _set_gpio_irqenable(bank, gpio, 1);
1108 static struct irq_chip mpuio_irq_chip = {
1110 .ack = mpuio_ack_irq,
1111 .mask = mpuio_mask_irq,
1112 .unmask = mpuio_unmask_irq,
1113 .set_type = gpio_irq_type,
1117 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1121 extern struct irq_chip mpuio_irq_chip;
1123 #define bank_is_mpuio(bank) 0
1127 /*---------------------------------------------------------------------*/
1129 static int initialized;
1130 static struct clk * gpio_ick;
1131 static struct clk * gpio_fck;
1133 #ifdef CONFIG_ARCH_OMAP2430
1134 static struct clk * gpio5_ick;
1135 static struct clk * gpio5_fck;
1138 static int __init _omap_gpio_init(void)
1141 struct gpio_bank *bank;
1145 if (cpu_is_omap15xx()) {
1146 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1147 if (IS_ERR(gpio_ick))
1148 printk("Could not get arm_gpio_ck\n");
1150 clk_enable(gpio_ick);
1152 if (cpu_is_omap24xx()) {
1153 gpio_ick = clk_get(NULL, "gpios_ick");
1154 if (IS_ERR(gpio_ick))
1155 printk("Could not get gpios_ick\n");
1157 clk_enable(gpio_ick);
1158 gpio_fck = clk_get(NULL, "gpios_fck");
1159 if (IS_ERR(gpio_fck))
1160 printk("Could not get gpios_fck\n");
1162 clk_enable(gpio_fck);
1165 * On 2430 GPIO 5 uses CORE L4 ICLK
1167 #ifdef CONFIG_ARCH_OMAP2430
1168 if (cpu_is_omap2430()) {
1169 gpio5_ick = clk_get(NULL, "gpio5_ick");
1170 if (IS_ERR(gpio5_ick))
1171 printk("Could not get gpio5_ick\n");
1173 clk_enable(gpio5_ick);
1174 gpio5_fck = clk_get(NULL, "gpio5_fck");
1175 if (IS_ERR(gpio5_fck))
1176 printk("Could not get gpio5_fck\n");
1178 clk_enable(gpio5_fck);
1183 #ifdef CONFIG_ARCH_OMAP15XX
1184 if (cpu_is_omap15xx()) {
1185 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1186 gpio_bank_count = 2;
1187 gpio_bank = gpio_bank_1510;
1190 #if defined(CONFIG_ARCH_OMAP16XX)
1191 if (cpu_is_omap16xx()) {
1194 gpio_bank_count = 5;
1195 gpio_bank = gpio_bank_1610;
1196 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1197 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1198 (rev >> 4) & 0x0f, rev & 0x0f);
1201 #ifdef CONFIG_ARCH_OMAP730
1202 if (cpu_is_omap730()) {
1203 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1204 gpio_bank_count = 7;
1205 gpio_bank = gpio_bank_730;
1209 #ifdef CONFIG_ARCH_OMAP24XX
1210 if (cpu_is_omap242x()) {
1213 gpio_bank_count = 4;
1214 gpio_bank = gpio_bank_242x;
1215 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1216 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1217 (rev >> 4) & 0x0f, rev & 0x0f);
1219 if (cpu_is_omap243x()) {
1222 gpio_bank_count = 5;
1223 gpio_bank = gpio_bank_243x;
1224 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1225 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1226 (rev >> 4) & 0x0f, rev & 0x0f);
1229 for (i = 0; i < gpio_bank_count; i++) {
1230 int j, gpio_count = 16;
1232 bank = &gpio_bank[i];
1233 bank->reserved_map = 0;
1234 bank->base = IO_ADDRESS(bank->base);
1235 spin_lock_init(&bank->lock);
1236 if (bank_is_mpuio(bank))
1237 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1238 #ifdef CONFIG_ARCH_OMAP15XX
1239 if (bank->method == METHOD_GPIO_1510) {
1240 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1241 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1244 #if defined(CONFIG_ARCH_OMAP16XX)
1245 if (bank->method == METHOD_GPIO_1610) {
1246 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1247 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1248 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1251 #ifdef CONFIG_ARCH_OMAP730
1252 if (bank->method == METHOD_GPIO_730) {
1253 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1254 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1256 gpio_count = 32; /* 730 has 32-bit GPIOs */
1259 #ifdef CONFIG_ARCH_OMAP24XX
1260 if (bank->method == METHOD_GPIO_24XX) {
1261 static const u32 non_wakeup_gpios[] = {
1262 0xe203ffc0, 0x08700040
1265 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1266 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1267 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1269 /* Initialize interface clock ungated, module enabled */
1270 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1271 if (i < ARRAY_SIZE(non_wakeup_gpios))
1272 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1276 for (j = bank->virtual_irq_start;
1277 j < bank->virtual_irq_start + gpio_count; j++) {
1278 if (bank_is_mpuio(bank))
1279 set_irq_chip(j, &mpuio_irq_chip);
1281 set_irq_chip(j, &gpio_irq_chip);
1282 set_irq_handler(j, handle_simple_irq);
1283 set_irq_flags(j, IRQF_VALID);
1285 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1286 set_irq_data(bank->irq, bank);
1289 /* Enable system clock for GPIO module.
1290 * The CAM_CLK_CTRL *is* really the right place. */
1291 if (cpu_is_omap16xx())
1292 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1294 #ifdef CONFIG_ARCH_OMAP24XX
1295 /* Enable autoidle for the OCP interface */
1296 if (cpu_is_omap24xx())
1297 omap_writel(1 << 0, 0x48019010);
1303 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1304 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1308 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1311 for (i = 0; i < gpio_bank_count; i++) {
1312 struct gpio_bank *bank = &gpio_bank[i];
1313 void __iomem *wake_status;
1314 void __iomem *wake_clear;
1315 void __iomem *wake_set;
1317 switch (bank->method) {
1318 #ifdef CONFIG_ARCH_OMAP16XX
1319 case METHOD_GPIO_1610:
1320 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1321 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1322 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1325 #ifdef CONFIG_ARCH_OMAP24XX
1326 case METHOD_GPIO_24XX:
1327 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1328 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1329 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1336 spin_lock(&bank->lock);
1337 bank->saved_wakeup = __raw_readl(wake_status);
1338 __raw_writel(0xffffffff, wake_clear);
1339 __raw_writel(bank->suspend_wakeup, wake_set);
1340 spin_unlock(&bank->lock);
1346 static int omap_gpio_resume(struct sys_device *dev)
1350 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1353 for (i = 0; i < gpio_bank_count; i++) {
1354 struct gpio_bank *bank = &gpio_bank[i];
1355 void __iomem *wake_clear;
1356 void __iomem *wake_set;
1358 switch (bank->method) {
1359 #ifdef CONFIG_ARCH_OMAP16XX
1360 case METHOD_GPIO_1610:
1361 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1362 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1365 #ifdef CONFIG_ARCH_OMAP24XX
1366 case METHOD_GPIO_24XX:
1367 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1368 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1375 spin_lock(&bank->lock);
1376 __raw_writel(0xffffffff, wake_clear);
1377 __raw_writel(bank->saved_wakeup, wake_set);
1378 spin_unlock(&bank->lock);
1384 static struct sysdev_class omap_gpio_sysclass = {
1385 set_kset_name("gpio"),
1386 .suspend = omap_gpio_suspend,
1387 .resume = omap_gpio_resume,
1390 static struct sys_device omap_gpio_device = {
1392 .cls = &omap_gpio_sysclass,
1397 #ifdef CONFIG_ARCH_OMAP24XX
1399 static int workaround_enabled;
1401 void omap2_gpio_prepare_for_retention(void)
1405 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1406 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1407 for (i = 0; i < gpio_bank_count; i++) {
1408 struct gpio_bank *bank = &gpio_bank[i];
1411 if (!(bank->enabled_non_wakeup_gpios))
1413 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1414 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1415 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1416 bank->saved_fallingdetect = l1;
1417 bank->saved_risingdetect = l2;
1418 l1 &= ~bank->enabled_non_wakeup_gpios;
1419 l2 &= ~bank->enabled_non_wakeup_gpios;
1420 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1421 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1425 workaround_enabled = 0;
1428 workaround_enabled = 1;
1431 void omap2_gpio_resume_after_retention(void)
1435 if (!workaround_enabled)
1437 for (i = 0; i < gpio_bank_count; i++) {
1438 struct gpio_bank *bank = &gpio_bank[i];
1441 if (!(bank->enabled_non_wakeup_gpios))
1443 __raw_writel(bank->saved_fallingdetect,
1444 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1445 __raw_writel(bank->saved_risingdetect,
1446 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1447 /* Check if any of the non-wakeup interrupt GPIOs have changed
1448 * state. If so, generate an IRQ by software. This is
1449 * horribly racy, but it's the best we can do to work around
1450 * this silicon bug. */
1451 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1452 l ^= bank->saved_datain;
1453 l &= bank->non_wakeup_gpios;
1457 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1458 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1459 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1460 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1461 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1462 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1471 * This may get called early from board specific init
1472 * for boards that have interrupts routed via FPGA.
1474 int __init omap_gpio_init(void)
1477 return _omap_gpio_init();
1482 static int __init omap_gpio_sysinit(void)
1487 ret = _omap_gpio_init();
1489 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1490 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1492 ret = sysdev_class_register(&omap_gpio_sysclass);
1494 ret = sysdev_register(&omap_gpio_device);
1502 EXPORT_SYMBOL(omap_request_gpio);
1503 EXPORT_SYMBOL(omap_free_gpio);
1504 EXPORT_SYMBOL(omap_set_gpio_direction);
1505 EXPORT_SYMBOL(omap_set_gpio_dataout);
1506 EXPORT_SYMBOL(omap_get_gpio_datain);
1508 arch_initcall(omap_gpio_sysinit);
1511 #ifdef CONFIG_DEBUG_FS
1513 #include <linux/debugfs.h>
1514 #include <linux/seq_file.h>
1516 static int gpio_is_input(struct gpio_bank *bank, int mask)
1518 void __iomem *reg = bank->base;
1520 switch (bank->method) {
1522 reg += OMAP_MPUIO_IO_CNTL;
1524 case METHOD_GPIO_1510:
1525 reg += OMAP1510_GPIO_DIR_CONTROL;
1527 case METHOD_GPIO_1610:
1528 reg += OMAP1610_GPIO_DIRECTION;
1530 case METHOD_GPIO_730:
1531 reg += OMAP730_GPIO_DIR_CONTROL;
1533 case METHOD_GPIO_24XX:
1534 reg += OMAP24XX_GPIO_OE;
1537 return __raw_readl(reg) & mask;
1541 static int dbg_gpio_show(struct seq_file *s, void *unused)
1543 unsigned i, j, gpio;
1545 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1546 struct gpio_bank *bank = gpio_bank + i;
1547 unsigned bankwidth = 16;
1550 if (bank_is_mpuio(bank))
1551 gpio = OMAP_MPUIO(0);
1552 else if (cpu_is_omap24xx() || cpu_is_omap730())
1555 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1556 unsigned irq, value, is_in, irqstat;
1558 if (!(bank->reserved_map & mask))
1561 irq = bank->virtual_irq_start + j;
1562 value = omap_get_gpio_datain(gpio);
1563 is_in = gpio_is_input(bank, mask);
1565 if (bank_is_mpuio(bank))
1566 seq_printf(s, "MPUIO %2d: ", j);
1568 seq_printf(s, "GPIO %3d: ", gpio);
1569 seq_printf(s, "%s %s",
1570 is_in ? "in " : "out",
1571 value ? "hi" : "lo");
1573 irqstat = irq_desc[irq].status;
1574 if (is_in && ((bank->suspend_wakeup & mask)
1575 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1576 char *trigger = NULL;
1578 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1579 case IRQ_TYPE_EDGE_FALLING:
1580 trigger = "falling";
1582 case IRQ_TYPE_EDGE_RISING:
1585 case IRQ_TYPE_EDGE_BOTH:
1586 trigger = "bothedge";
1588 case IRQ_TYPE_LEVEL_LOW:
1591 case IRQ_TYPE_LEVEL_HIGH:
1595 trigger = "(unspecified)";
1598 seq_printf(s, ", irq-%d %s%s",
1600 (bank->suspend_wakeup & mask)
1603 seq_printf(s, "\n");
1606 if (bank_is_mpuio(bank)) {
1607 seq_printf(s, "\n");
1614 static int dbg_gpio_open(struct inode *inode, struct file *file)
1616 return single_open(file, dbg_gpio_show, &inode->i_private);
1619 static const struct file_operations debug_fops = {
1620 .open = dbg_gpio_open,
1622 .llseek = seq_lseek,
1623 .release = single_release,
1626 static int __init omap_gpio_debuginit(void)
1628 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1629 NULL, NULL, &debug_fops);
1632 late_initcall(omap_gpio_debuginit);