arch/arm/plat-omap/include/mach/mcbsp.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mcbsp.h
   3  *
   4  * Defines for Multi-Channel Buffered Serial Port
   5  *
   6  * Copyright (C) 2002 RidgeRun, Inc.
   7  * Author: Steve Johnson
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22  *
  23  */
  24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
  25 #define __ASM_ARCH_OMAP_MCBSP_H
  26
  27 #include <linux/completion.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <mach/hardware.h>
  31 #include <mach/clock.h>
  32
  33 #define OMAP730_MCBSP1_BASE     0xfffb1000
  34 #define OMAP730_MCBSP2_BASE     0xfffb1800
  35
  36 #define OMAP1510_MCBSP1_BASE    0xe1011800
  37 #define OMAP1510_MCBSP2_BASE    0xfffb1000
  38 #define OMAP1510_MCBSP3_BASE    0xe1017000
  39
  40 #define OMAP1610_MCBSP1_BASE    0xe1011800
  41 #define OMAP1610_MCBSP2_BASE    0xfffb1000
  42 #define OMAP1610_MCBSP3_BASE    0xe1017000
  43
  44 #define OMAP24XX_MCBSP1_BASE    0x48074000
  45 #define OMAP24XX_MCBSP2_BASE    0x48076000
  46
  47 #define OMAP34XX_MCBSP1_BASE    0x48074000
  48 #define OMAP34XX_MCBSP2_BASE    0x49022000
  49
  50 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
  51
  52 #define OMAP_MCBSP_REG_DRR2     0x00
  53 #define OMAP_MCBSP_REG_DRR1     0x02
  54 #define OMAP_MCBSP_REG_DXR2     0x04
  55 #define OMAP_MCBSP_REG_DXR1     0x06
  56 #define OMAP_MCBSP_REG_SPCR2    0x08
  57 #define OMAP_MCBSP_REG_SPCR1    0x0a
  58 #define OMAP_MCBSP_REG_RCR2     0x0c
  59 #define OMAP_MCBSP_REG_RCR1     0x0e
  60 #define OMAP_MCBSP_REG_XCR2     0x10
  61 #define OMAP_MCBSP_REG_XCR1     0x12
  62 #define OMAP_MCBSP_REG_SRGR2    0x14
  63 #define OMAP_MCBSP_REG_SRGR1    0x16
  64 #define OMAP_MCBSP_REG_MCR2     0x18
  65 #define OMAP_MCBSP_REG_MCR1     0x1a
  66 #define OMAP_MCBSP_REG_RCERA    0x1c
  67 #define OMAP_MCBSP_REG_RCERB    0x1e
  68 #define OMAP_MCBSP_REG_XCERA    0x20
  69 #define OMAP_MCBSP_REG_XCERB    0x22
  70 #define OMAP_MCBSP_REG_PCR0     0x24
  71 #define OMAP_MCBSP_REG_RCERC    0x26
  72 #define OMAP_MCBSP_REG_RCERD    0x28
  73 #define OMAP_MCBSP_REG_XCERC    0x2A
  74 #define OMAP_MCBSP_REG_XCERD    0x2C
  75 #define OMAP_MCBSP_REG_RCERE    0x2E
  76 #define OMAP_MCBSP_REG_RCERF    0x30
  77 #define OMAP_MCBSP_REG_XCERE    0x32
  78 #define OMAP_MCBSP_REG_XCERF    0x34
  79 #define OMAP_MCBSP_REG_RCERG    0x36
  80 #define OMAP_MCBSP_REG_RCERH    0x38
  81 #define OMAP_MCBSP_REG_XCERG    0x3A
  82 #define OMAP_MCBSP_REG_XCERH    0x3C
  83
  84 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
  85 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
  86
  87 #define AUDIO_MCBSP             OMAP_MCBSP1
  88 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
  89 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
  90
  91 #elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  92
  93 #define OMAP_MCBSP_REG_DRR2     0x00
  94 #define OMAP_MCBSP_REG_DRR1     0x04
  95 #define OMAP_MCBSP_REG_DXR2     0x08
  96 #define OMAP_MCBSP_REG_DXR1     0x0C
  97 #define OMAP_MCBSP_REG_DRR      0x00
  98 #define OMAP_MCBSP_REG_DXR      0x08
  99 #define OMAP_MCBSP_REG_SPCR2    0x10
 100 #define OMAP_MCBSP_REG_SPCR1    0x14
 101 #define OMAP_MCBSP_REG_RCR2     0x18
 102 #define OMAP_MCBSP_REG_RCR1     0x1C
 103 #define OMAP_MCBSP_REG_XCR2     0x20
 104 #define OMAP_MCBSP_REG_XCR1     0x24
 105 #define OMAP_MCBSP_REG_SRGR2    0x28
 106 #define OMAP_MCBSP_REG_SRGR1    0x2C
 107 #define OMAP_MCBSP_REG_MCR2     0x30
 108 #define OMAP_MCBSP_REG_MCR1     0x34
 109 #define OMAP_MCBSP_REG_RCERA    0x38
 110 #define OMAP_MCBSP_REG_RCERB    0x3C
 111 #define OMAP_MCBSP_REG_XCERA    0x40
 112 #define OMAP_MCBSP_REG_XCERB    0x44
 113 #define OMAP_MCBSP_REG_PCR0     0x48
 114 #define OMAP_MCBSP_REG_RCERC    0x4C
 115 #define OMAP_MCBSP_REG_RCERD    0x50
 116 #define OMAP_MCBSP_REG_XCERC    0x54
 117 #define OMAP_MCBSP_REG_XCERD    0x58
 118 #define OMAP_MCBSP_REG_RCERE    0x5C
 119 #define OMAP_MCBSP_REG_RCERF    0x60
 120 #define OMAP_MCBSP_REG_XCERE    0x64
 121 #define OMAP_MCBSP_REG_XCERF    0x68
 122 #define OMAP_MCBSP_REG_RCERG    0x6C
 123 #define OMAP_MCBSP_REG_RCERH    0x70
 124 #define OMAP_MCBSP_REG_XCERG    0x74
 125 #define OMAP_MCBSP_REG_XCERH    0x78
 126 #define OMAP_MCBSP_REG_SYSCON   0x8C
 127 #define OMAP_MCBSP_REG_XCCR     0xAC
 128 #define OMAP_MCBSP_REG_RCCR     0xB0
 129
 130 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 131 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
 132
 133 #define AUDIO_MCBSP             OMAP_MCBSP2
 134 #define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
 135 #define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
 136
 137 #endif
 138
 139 /************************** McBSP SPCR1 bit definitions ***********************/
 140 #define RRST                    0x0001
 141 #define RRDY                    0x0002
 142 #define RFULL                   0x0004
 143 #define RSYNC_ERR               0x0008
 144 #define RINTM(value)            ((value)<<4)    /* bits 4:5 */
 145 #define ABIS                    0x0040
 146 #define DXENA                   0x0080
 147 #define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
 148 #define RJUST(value)            ((value)<<13)   /* bits 13:14 */
 149 #define ALB                     0x8000
 150 #define DLB                     0x8000
 151
 152 /************************** McBSP SPCR2 bit definitions ***********************/
 153 #define XRST            0x0001
 154 #define XRDY            0x0002
 155 #define XEMPTY          0x0004
 156 #define XSYNC_ERR       0x0008
 157 #define XINTM(value)    ((value)<<4)            /* bits 4:5 */
 158 #define GRST            0x0040
 159 #define FRST            0x0080
 160 #define SOFT            0x0100
 161 #define FREE            0x0200
 162
 163 /************************** McBSP PCR bit definitions *************************/
 164 #define CLKRP           0x0001
 165 #define CLKXP           0x0002
 166 #define FSRP            0x0004
 167 #define FSXP            0x0008
 168 #define DR_STAT         0x0010
 169 #define DX_STAT         0x0020
 170 #define CLKS_STAT       0x0040
 171 #define SCLKME          0x0080
 172 #define CLKRM           0x0100
 173 #define CLKXM           0x0200
 174 #define FSRM            0x0400
 175 #define FSXM            0x0800
 176 #define RIOEN           0x1000
 177 #define XIOEN           0x2000
 178 #define IDLE_EN         0x4000
 179
 180 /************************** McBSP RCR1 bit definitions ************************/
 181 #define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 182 #define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 183
 184 /************************** McBSP XCR1 bit definitions ************************/
 185 #define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 186 #define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 187
 188 /*************************** McBSP RCR2 bit definitions ***********************/
 189 #define RDATDLY(value)          (value)         /* Bits 0:1 */
 190 #define RFIG                    0x0004
 191 #define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 192 #define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 193 #define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 194 #define RPHASE                  0x8000
 195
 196 /*************************** McBSP XCR2 bit definitions ***********************/
 197 #define XDATDLY(value)          (value)         /* Bits 0:1 */
 198 #define XFIG                    0x0004
 199 #define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 200 #define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 201 #define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 202 #define XPHASE                  0x8000
 203
 204 /************************* McBSP SRGR1 bit definitions ************************/
 205 #define CLKGDV(value)           (value)         /* Bits 0:7 */
 206 #define FWID(value)             ((value)<<8)    /* Bits 8:15 */
 207
 208 /************************* McBSP SRGR2 bit definitions ************************/
 209 #define FPER(value)             (value)         /* Bits 0:11 */
 210 #define FSGM                    0x1000
 211 #define CLKSM                   0x2000
 212 #define CLKSP                   0x4000
 213 #define GSYNC                   0x8000
 214
 215 /************************* McBSP MCR1 bit definitions *************************/
 216 #define RMCM                    0x0001
 217 #define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 218 #define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 219 #define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 220
 221 /************************* McBSP MCR2 bit definitions *************************/
 222 #define XMCM(value)             (value)         /* Bits 0:1 */
 223 #define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 224 #define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 225 #define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 226
 227 /*********************** McBSP XCCR bit definitions *************************/
 228 #define DILB                    0x0020
 229 #define XDMAEN                  0x0008
 230 #define XDISABLE                0x0001
 231
 232 /********************** McBSP RCCR bit definitions *************************/
 233 #define RDMAEN                  0x0008
 234 #define RDISABLE                0x0001
 235
 236 /********************** McBSP SYSCONFIG bit definitions ********************/
 237 #define SOFTRST                 0x0002
 238
 239 /* we don't do multichannel for now */
 240 struct omap_mcbsp_reg_cfg {
 241         u16 spcr2;
 242         u16 spcr1;
 243         u16 rcr2;
 244         u16 rcr1;
 245         u16 xcr2;
 246         u16 xcr1;
 247         u16 srgr2;
 248         u16 srgr1;
 249         u16 mcr2;
 250         u16 mcr1;
 251         u16 pcr0;
 252         u16 rcerc;
 253         u16 rcerd;
 254         u16 xcerc;
 255         u16 xcerd;
 256         u16 rcere;
 257         u16 rcerf;
 258         u16 xcere;
 259         u16 xcerf;
 260         u16 rcerg;
 261         u16 rcerh;
 262         u16 xcerg;
 263         u16 xcerh;
 264 };
 265
 266 typedef enum {
 267         OMAP_MCBSP1 = 0,
 268         OMAP_MCBSP2,
 269         OMAP_MCBSP3,
 270 } omap_mcbsp_id;
 271
 272 typedef int __bitwise omap_mcbsp_io_type_t;
 273 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
 274 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
 275
 276 typedef enum {
 277         OMAP_MCBSP_WORD_8 = 0,
 278         OMAP_MCBSP_WORD_12,
 279         OMAP_MCBSP_WORD_16,
 280         OMAP_MCBSP_WORD_20,
 281         OMAP_MCBSP_WORD_24,
 282         OMAP_MCBSP_WORD_32,
 283 } omap_mcbsp_word_length;
 284
 285 typedef enum {
 286         OMAP_MCBSP_CLK_RISING = 0,
 287         OMAP_MCBSP_CLK_FALLING,
 288 } omap_mcbsp_clk_polarity;
 289
 290 typedef enum {
 291         OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
 292         OMAP_MCBSP_FS_ACTIVE_LOW,
 293 } omap_mcbsp_fs_polarity;
 294
 295 typedef enum {
 296         OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
 297         OMAP_MCBSP_CLK_STP_MODE_DELAY,
 298 } omap_mcbsp_clk_stp_mode;
 299
 300
 301 /******* SPI specific mode **********/
 302 typedef enum {
 303         OMAP_MCBSP_SPI_MASTER = 0,
 304         OMAP_MCBSP_SPI_SLAVE,
 305 } omap_mcbsp_spi_mode;
 306
 307 struct omap_mcbsp_spi_cfg {
 308         omap_mcbsp_spi_mode             spi_mode;
 309         omap_mcbsp_clk_polarity         rx_clock_polarity;
 310         omap_mcbsp_clk_polarity         tx_clock_polarity;
 311         omap_mcbsp_fs_polarity          fsx_polarity;
 312         u8                              clk_div;
 313         omap_mcbsp_clk_stp_mode         clk_stp_mode;
 314         omap_mcbsp_word_length          word_length;
 315 };
 316
 317 /* Platform specific configuration */
 318 struct omap_mcbsp_ops {
 319         void (*request)(unsigned int);
 320         void (*free)(unsigned int);
 321 };
 322
 323 struct omap_mcbsp_platform_data {
 324         unsigned long phys_base;
 325         u8 dma_rx_sync, dma_tx_sync;
 326         u16 rx_irq, tx_irq;
 327         struct omap_mcbsp_ops *ops;
 328         char const *clk_name;
 329 };
 330
 331 struct omap_mcbsp {
 332         struct device *dev;
 333         unsigned long phys_base;
 334         void __iomem *io_base;
 335         u8 id;
 336         u8 free;
 337         omap_mcbsp_word_length rx_word_length;
 338         omap_mcbsp_word_length tx_word_length;
 339
 340         omap_mcbsp_io_type_t io_type; /* IRQ or poll */
 341         /* IRQ based TX/RX */
 342         int rx_irq;
 343         int tx_irq;
 344
 345         /* DMA stuff */
 346         u8 dma_rx_sync;
 347         short dma_rx_lch;
 348         u8 dma_tx_sync;
 349         short dma_tx_lch;
 350
 351         /* Completion queues */
 352         struct completion tx_irq_completion;
 353         struct completion rx_irq_completion;
 354         struct completion tx_dma_completion;
 355         struct completion rx_dma_completion;
 356
 357         /* Protect the field .free, while checking if the mcbsp is in use */
 358         spinlock_t lock;
 359         struct omap_mcbsp_platform_data *pdata;
 360         struct clk *clk;
 361 };
 362 extern struct omap_mcbsp **mcbsp_ptr;
 363 extern int omap_mcbsp_count;
 364
 365 int omap_mcbsp_init(void);
 366 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 367                                         int size);
 368 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 369 int omap_mcbsp_request(unsigned int id);
 370 void omap_mcbsp_free(unsigned int id);
 371 void omap_mcbsp_start(unsigned int id);
 372 void omap_mcbsp_stop(unsigned int id);
 373 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
 374 u32 omap_mcbsp_recv_word(unsigned int id);
 375
 376 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 377 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 378 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
 379 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
 380
 381
 382 /* SPI specific API */
 383 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
 384
 385 /* Polled read/write functions */
 386 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 387 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 388 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 389
 390 #endif