arch/arm/plat-omap/include/mach/pm.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/pm.h
   3  *
   4  * Header file for OMAP Power Management Routines
   5  *
   6  * Author: MontaVista Software, Inc.
   7  *         support@mvista.com
   8  *
   9  * Copyright 2002 MontaVista Software Inc.
  10  *
  11  * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under the terms of the GNU General Public License as published by the
  15  * Free Software Foundation; either version 2 of the License, or (at your
  16  * option) any later version.
  17  *
  18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  19  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  21  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  24  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * You should have received a copy of the GNU General Public License along
  30  * with this program; if not, write to the Free Software Foundation, Inc.,
  31  * 675 Mass Ave, Cambridge, MA 02139, USA.
  32  */
  33
  34 #ifndef __ASM_ARCH_OMAP_PM_H
  35 #define __ASM_ARCH_OMAP_PM_H
  36
  37 /*
  38  * ----------------------------------------------------------------------------
  39  * Register and offset definitions to be used in PM assembler code
  40  * ----------------------------------------------------------------------------
  41  */
  42 #define CLKGEN_REG_ASM_BASE             IO_ADDRESS(0xfffece00)
  43 #define ARM_IDLECT1_ASM_OFFSET          0x04
  44 #define ARM_IDLECT2_ASM_OFFSET          0x08
  45
  46 #define TCMIF_ASM_BASE                  IO_ADDRESS(0xfffecc00)
  47 #define EMIFS_CONFIG_ASM_OFFSET         0x0c
  48 #define EMIFF_SDRAM_CONFIG_ASM_OFFSET   0x20
  49
  50 /*
  51  * ----------------------------------------------------------------------------
  52  * Power management bitmasks
  53  * ----------------------------------------------------------------------------
  54  */
  55 #define IDLE_WAIT_CYCLES                0x00000fff
  56 #define PERIPHERAL_ENABLE               0x2
  57
  58 #define SELF_REFRESH_MODE               0x0c000001
  59 #define IDLE_EMIFS_REQUEST              0xc
  60 #define MODEM_32K_EN                    0x1
  61 #define PER_EN                          0x1
  62
  63 #define CPU_SUSPEND_SIZE                200
  64 #define ULPD_LOW_PWR_EN                 0x0001
  65 #define ULPD_DEEP_SLEEP_TRANSITION_EN   0x0010
  66 #define ULPD_SETUP_ANALOG_CELL_3_VAL    0
  67 #define ULPD_POWER_CTRL_REG_VAL         0x0219
  68
  69 #define DSP_IDLE_DELAY                  10
  70 #define DSP_IDLE                        0x0040
  71 #define DSP_RST                         0x0004
  72 #define DSP_ENABLE                      0x0002
  73 #define SUFFICIENT_DSP_RESET_TIME       1000
  74 #define DEFAULT_MPUI_CONFIG             0x05cf
  75 #define ENABLE_XORCLK                   0x2
  76 #define DSP_CLOCK_ENABLE                0x2000
  77 #define DSP_IDLE_MODE                   0x2
  78 #define TC_IDLE_REQUEST                 (0x0000000c)
  79
  80 #define IRQ_LEVEL2                      (1<<0)
  81 #define IRQ_KEYBOARD                    (1<<1)
  82 #define IRQ_UART2                       (1<<15)
  83
  84 #define PDE_BIT                         0x08
  85 #define PWD_EN_BIT                      0x04
  86 #define EN_PERCK_BIT                    0x04
  87
  88 #define OMAP1510_DEEP_SLEEP_REQUEST     0x0ec7
  89 #define OMAP1510_BIG_SLEEP_REQUEST      0x0cc5
  90 #define OMAP1510_IDLE_LOOP_REQUEST      0x0c00
  91 #define OMAP1510_IDLE_CLOCK_DOMAINS     0x2
  92
  93 /* Both big sleep and deep sleep use same values. Difference is in ULPD. */
  94 #define OMAP1610_IDLECT1_SLEEP_VAL      0x13c7
  95 #define OMAP1610_IDLECT2_SLEEP_VAL      0x09c7
  96 #define OMAP1610_IDLECT3_VAL            0x3f
  97 #define OMAP1610_IDLECT3_SLEEP_ORMASK   0x2c
  98 #define OMAP1610_IDLECT3                0xfffece24
  99 #define OMAP1610_IDLE_LOOP_REQUEST      0x0400
 100
 101 #define OMAP730_IDLECT1_SLEEP_VAL       0x16c7
 102 #define OMAP730_IDLECT2_SLEEP_VAL       0x09c7
 103 #define OMAP730_IDLECT3_VAL             0x3f
 104 #define OMAP730_IDLECT3         0xfffece24
 105 #define OMAP730_IDLE_LOOP_REQUEST       0x0C00
 106
 107 #if     !defined(CONFIG_ARCH_OMAP730) && \
 108         !defined(CONFIG_ARCH_OMAP15XX) && \
 109         !defined(CONFIG_ARCH_OMAP16XX) && \
 110         !defined(CONFIG_ARCH_OMAP24XX)
 111 #error "Power management for this processor not implemented yet"
 112 #endif
 113
 114 #ifndef __ASSEMBLER__
 115
 116 #include <linux/clk.h>
 117
 118 extern void prevent_idle_sleep(void);
 119 extern void allow_idle_sleep(void);
 120
 121 /**
 122  * clk_deny_idle - Prevents the clock from being idled during MPU idle
 123  * @clk: clock signal handle
 124  */
 125 void clk_deny_idle(struct clk *clk);
 126
 127 /**
 128  * clk_allow_idle - Counters previous clk_deny_idle
 129  * @clk: clock signal handle
 130  */
 131 void clk_deny_idle(struct clk *clk);
 132
 133 extern void omap_pm_idle(void);
 134 extern void omap_pm_suspend(void);
 135 extern void omap730_cpu_suspend(unsigned short, unsigned short);
 136 extern void omap1510_cpu_suspend(unsigned short, unsigned short);
 137 extern void omap1610_cpu_suspend(unsigned short, unsigned short);
 138 extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
 139                                         void __iomem *sdrc_power);
 140 extern void omap730_idle_loop_suspend(void);
 141 extern void omap1510_idle_loop_suspend(void);
 142 extern void omap1610_idle_loop_suspend(void);
 143 extern void omap24xx_idle_loop_suspend(void);
 144
 145 extern unsigned int omap730_cpu_suspend_sz;
 146 extern unsigned int omap1510_cpu_suspend_sz;
 147 extern unsigned int omap1610_cpu_suspend_sz;
 148 extern unsigned int omap24xx_cpu_suspend_sz;
 149 extern unsigned int omap730_idle_loop_suspend_sz;
 150 extern unsigned int omap1510_idle_loop_suspend_sz;
 151 extern unsigned int omap1610_idle_loop_suspend_sz;
 152 extern unsigned int omap24xx_idle_loop_suspend_sz;
 153
 154 #ifdef CONFIG_OMAP_SERIAL_WAKE
 155 extern void omap_serial_wake_trigger(int enable);
 156 #else
 157 #define omap_serial_wakeup_init()       {}
 158 #define omap_serial_wake_trigger(x)     {}
 159 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
 160
 161 #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
 162 #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
 163 #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
 164
 165 #define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
 166 #define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
 167 #define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
 168
 169 #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
 170 #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
 171 #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
 172
 173 #define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
 174 #define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
 175 #define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
 176
 177 #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
 178 #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
 179 #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
 180
 181 #define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
 182 #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
 183 #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
 184
 185 #define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
 186 #define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
 187 #define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
 188
 189 /*
 190  * List of global OMAP registers to preserve.
 191  * More ones like CP and general purpose register values are preserved
 192  * with the stack pointer in sleep.S.
 193  */
 194
 195 enum arm_save_state {
 196         ARM_SLEEP_SAVE_START = 0,
 197         /*
 198          * MPU control registers 32 bits
 199          */
 200         ARM_SLEEP_SAVE_ARM_CKCTL,
 201         ARM_SLEEP_SAVE_ARM_IDLECT1,
 202         ARM_SLEEP_SAVE_ARM_IDLECT2,
 203         ARM_SLEEP_SAVE_ARM_IDLECT3,
 204         ARM_SLEEP_SAVE_ARM_EWUPCT,
 205         ARM_SLEEP_SAVE_ARM_RSTCT1,
 206         ARM_SLEEP_SAVE_ARM_RSTCT2,
 207         ARM_SLEEP_SAVE_ARM_SYSST,
 208         ARM_SLEEP_SAVE_SIZE
 209 };
 210
 211 enum dsp_save_state {
 212         DSP_SLEEP_SAVE_START = 0,
 213         /*
 214          * DSP registers 16 bits
 215          */
 216         DSP_SLEEP_SAVE_DSP_IDLECT2,
 217         DSP_SLEEP_SAVE_SIZE
 218 };
 219
 220 enum ulpd_save_state {
 221         ULPD_SLEEP_SAVE_START = 0,
 222         /*
 223          * ULPD registers 16 bits
 224          */
 225         ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
 226         ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
 227         ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
 228         ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
 229         ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
 230         ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
 231         ULPD_SLEEP_SAVE_SIZE
 232 };
 233
 234 enum mpui1510_save_state {
 235         MPUI1510_SLEEP_SAVE_START = 0,
 236         /*
 237          * MPUI registers 32 bits
 238          */
 239         MPUI1510_SLEEP_SAVE_MPUI_CTRL,
 240         MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
 241         MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
 242         MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
 243         MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
 244         MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
 245         MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
 246         MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
 247 #if defined(CONFIG_ARCH_OMAP15XX)
 248         MPUI1510_SLEEP_SAVE_SIZE
 249 #else
 250         MPUI1510_SLEEP_SAVE_SIZE = 0
 251 #endif
 252 };
 253
 254 enum mpui730_save_state {
 255         MPUI730_SLEEP_SAVE_START = 0,
 256         /*
 257          * MPUI registers 32 bits
 258          */
 259         MPUI730_SLEEP_SAVE_MPUI_CTRL,
 260         MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
 261         MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
 262         MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
 263         MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
 264         MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
 265         MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
 266         MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
 267         MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
 268 #if defined(CONFIG_ARCH_OMAP730)
 269         MPUI730_SLEEP_SAVE_SIZE
 270 #else
 271         MPUI730_SLEEP_SAVE_SIZE = 0
 272 #endif
 273 };
 274
 275 enum mpui1610_save_state {
 276         MPUI1610_SLEEP_SAVE_START = 0,
 277         /*
 278          * MPUI registers 32 bits
 279          */
 280         MPUI1610_SLEEP_SAVE_MPUI_CTRL,
 281         MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
 282         MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
 283         MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
 284         MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
 285         MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
 286         MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
 287         MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
 288         MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
 289         MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
 290         MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
 291 #if defined(CONFIG_ARCH_OMAP16XX)
 292         MPUI1610_SLEEP_SAVE_SIZE
 293 #else
 294         MPUI1610_SLEEP_SAVE_SIZE = 0
 295 #endif
 296 };
 297
 298 enum omap24xx_save_state {
 299         OMAP24XX_SLEEP_SAVE_START = 0,
 300         OMAP24XX_SLEEP_SAVE_INTC_MIR0,
 301         OMAP24XX_SLEEP_SAVE_INTC_MIR1,
 302         OMAP24XX_SLEEP_SAVE_INTC_MIR2,
 303
 304         OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
 305         OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
 306         OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
 307         OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
 308         OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
 309
 310         OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
 311         OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
 312         OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
 313         OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
 314         OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
 315
 316         OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
 317         OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
 318         OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
 319         OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
 320         OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
 321         OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
 322         OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
 323         OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
 324         OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
 325
 326         OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
 327         OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
 328         OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
 329         OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
 330         OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
 331         OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
 332         OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
 333         OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
 334
 335         OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
 336         OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
 337         OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
 338         OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
 339         OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
 340         OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
 341         OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
 342         OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
 343         OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
 344         OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
 345         OMAP24XX_SLEEP_SAVE_GPIO3_OE,
 346         OMAP24XX_SLEEP_SAVE_GPIO4_OE,
 347         OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
 348         OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
 349         OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
 350         OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
 351         OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
 352         OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
 353         OMAP24XX_SLEEP_SAVE_SIZE
 354 };
 355
 356 #endif /* ASSEMBLER */
 357 #endif /* __ASM_ARCH_OMAP_PM_H */