2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/spi/spi.h>
16 #include <asm/arch/at32ap7000.h>
17 #include <asm/arch/board.h>
18 #include <asm/arch/portmux.h>
19 #include <asm/arch/sm.h>
21 #include <video/atmel_lcdc.h>
31 .end = base + 0x3ff, \
32 .flags = IORESOURCE_MEM, \
38 .flags = IORESOURCE_IRQ, \
40 #define NAMED_IRQ(num, _name) \
45 .flags = IORESOURCE_IRQ, \
48 #define DEFINE_DEV(_name, _id) \
49 static struct platform_device _name##_id##_device = { \
52 .resource = _name##_id##_resource, \
53 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
55 #define DEFINE_DEV_DATA(_name, _id) \
56 static struct platform_device _name##_id##_device = { \
60 .platform_data = &_name##_id##_data, \
62 .resource = _name##_id##_resource, \
63 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
66 #define select_peripheral(pin, periph, flags) \
67 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
69 #define DEV_CLK(_name, devname, bus, _index) \
70 static struct clk devname##_##_name = { \
72 .dev = &devname##_device.dev, \
73 .parent = &bus##_clk, \
74 .mode = bus##_clk_mode, \
75 .get_rate = bus##_clk_get_rate, \
79 unsigned long at32ap7000_osc_rates[3] = {
81 /* FIXME: these are ATSTK1002-specific */
86 static unsigned long osc_get_rate(struct clk *clk)
88 return at32ap7000_osc_rates[clk->index];
91 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
93 unsigned long div, mul, rate;
95 if (!(control & SM_BIT(PLLEN)))
98 div = SM_BFEXT(PLLDIV, control) + 1;
99 mul = SM_BFEXT(PLLMUL, control) + 1;
101 rate = clk->parent->get_rate(clk->parent);
102 rate = (rate + div / 2) / div;
108 static unsigned long pll0_get_rate(struct clk *clk)
112 control = sm_readl(&system_manager, PM_PLL0);
114 return pll_get_rate(clk, control);
117 static unsigned long pll1_get_rate(struct clk *clk)
121 control = sm_readl(&system_manager, PM_PLL1);
123 return pll_get_rate(clk, control);
127 * The AT32AP7000 has five primary clock sources: One 32kHz
128 * oscillator, two crystal oscillators and two PLLs.
130 static struct clk osc32k = {
132 .get_rate = osc_get_rate,
136 static struct clk osc0 = {
138 .get_rate = osc_get_rate,
142 static struct clk osc1 = {
144 .get_rate = osc_get_rate,
147 static struct clk pll0 = {
149 .get_rate = pll0_get_rate,
152 static struct clk pll1 = {
154 .get_rate = pll1_get_rate,
159 * The main clock can be either osc0 or pll0. The boot loader may
160 * have chosen one for us, so we don't really know which one until we
161 * have a look at the SM.
163 static struct clk *main_clock;
166 * Synchronous clocks are generated from the main clock. The clocks
167 * must satisfy the constraint
168 * fCPU >= fHSB >= fPB
169 * i.e. each clock must not be faster than its parent.
171 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
173 return main_clock->get_rate(main_clock) >> shift;
176 static void cpu_clk_mode(struct clk *clk, int enabled)
178 struct at32_sm *sm = &system_manager;
182 spin_lock_irqsave(&sm->lock, flags);
183 mask = sm_readl(sm, PM_CPU_MASK);
185 mask |= 1 << clk->index;
187 mask &= ~(1 << clk->index);
188 sm_writel(sm, PM_CPU_MASK, mask);
189 spin_unlock_irqrestore(&sm->lock, flags);
192 static unsigned long cpu_clk_get_rate(struct clk *clk)
194 unsigned long cksel, shift = 0;
196 cksel = sm_readl(&system_manager, PM_CKSEL);
197 if (cksel & SM_BIT(CPUDIV))
198 shift = SM_BFEXT(CPUSEL, cksel) + 1;
200 return bus_clk_get_rate(clk, shift);
203 static void hsb_clk_mode(struct clk *clk, int enabled)
205 struct at32_sm *sm = &system_manager;
209 spin_lock_irqsave(&sm->lock, flags);
210 mask = sm_readl(sm, PM_HSB_MASK);
212 mask |= 1 << clk->index;
214 mask &= ~(1 << clk->index);
215 sm_writel(sm, PM_HSB_MASK, mask);
216 spin_unlock_irqrestore(&sm->lock, flags);
219 static unsigned long hsb_clk_get_rate(struct clk *clk)
221 unsigned long cksel, shift = 0;
223 cksel = sm_readl(&system_manager, PM_CKSEL);
224 if (cksel & SM_BIT(HSBDIV))
225 shift = SM_BFEXT(HSBSEL, cksel) + 1;
227 return bus_clk_get_rate(clk, shift);
230 static void pba_clk_mode(struct clk *clk, int enabled)
232 struct at32_sm *sm = &system_manager;
236 spin_lock_irqsave(&sm->lock, flags);
237 mask = sm_readl(sm, PM_PBA_MASK);
239 mask |= 1 << clk->index;
241 mask &= ~(1 << clk->index);
242 sm_writel(sm, PM_PBA_MASK, mask);
243 spin_unlock_irqrestore(&sm->lock, flags);
246 static unsigned long pba_clk_get_rate(struct clk *clk)
248 unsigned long cksel, shift = 0;
250 cksel = sm_readl(&system_manager, PM_CKSEL);
251 if (cksel & SM_BIT(PBADIV))
252 shift = SM_BFEXT(PBASEL, cksel) + 1;
254 return bus_clk_get_rate(clk, shift);
257 static void pbb_clk_mode(struct clk *clk, int enabled)
259 struct at32_sm *sm = &system_manager;
263 spin_lock_irqsave(&sm->lock, flags);
264 mask = sm_readl(sm, PM_PBB_MASK);
266 mask |= 1 << clk->index;
268 mask &= ~(1 << clk->index);
269 sm_writel(sm, PM_PBB_MASK, mask);
270 spin_unlock_irqrestore(&sm->lock, flags);
273 static unsigned long pbb_clk_get_rate(struct clk *clk)
275 unsigned long cksel, shift = 0;
277 cksel = sm_readl(&system_manager, PM_CKSEL);
278 if (cksel & SM_BIT(PBBDIV))
279 shift = SM_BFEXT(PBBSEL, cksel) + 1;
281 return bus_clk_get_rate(clk, shift);
284 static struct clk cpu_clk = {
286 .get_rate = cpu_clk_get_rate,
289 static struct clk hsb_clk = {
292 .get_rate = hsb_clk_get_rate,
294 static struct clk pba_clk = {
297 .mode = hsb_clk_mode,
298 .get_rate = pba_clk_get_rate,
301 static struct clk pbb_clk = {
304 .mode = hsb_clk_mode,
305 .get_rate = pbb_clk_get_rate,
310 /* --------------------------------------------------------------------
311 * Generic Clock operations
312 * -------------------------------------------------------------------- */
314 static void genclk_mode(struct clk *clk, int enabled)
318 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
320 control |= SM_BIT(CEN);
322 control &= ~SM_BIT(CEN);
323 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
326 static unsigned long genclk_get_rate(struct clk *clk)
329 unsigned long div = 1;
331 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
332 if (control & SM_BIT(DIVEN))
333 div = 2 * (SM_BFEXT(DIV, control) + 1);
335 return clk->parent->get_rate(clk->parent) / div;
338 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
341 unsigned long parent_rate, actual_rate, div;
343 parent_rate = clk->parent->get_rate(clk->parent);
344 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
346 if (rate > 3 * parent_rate / 4) {
347 actual_rate = parent_rate;
348 control &= ~SM_BIT(DIVEN);
350 div = (parent_rate + rate) / (2 * rate) - 1;
351 control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
352 actual_rate = parent_rate / (2 * (div + 1));
355 printk("clk %s: new rate %lu (actual rate %lu)\n",
356 clk->name, rate, actual_rate);
359 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
365 int genclk_set_parent(struct clk *clk, struct clk *parent)
369 printk("clk %s: new parent %s (was %s)\n",
370 clk->name, parent->name, clk->parent->name);
372 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
374 if (parent == &osc1 || parent == &pll1)
375 control |= SM_BIT(OSCSEL);
376 else if (parent == &osc0 || parent == &pll0)
377 control &= ~SM_BIT(OSCSEL);
381 if (parent == &pll0 || parent == &pll1)
382 control |= SM_BIT(PLLSEL);
384 control &= ~SM_BIT(PLLSEL);
386 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
387 clk->parent = parent;
392 static void __init genclk_init_parent(struct clk *clk)
397 BUG_ON(clk->index > 7);
399 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
400 if (control & SM_BIT(OSCSEL))
401 parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
403 parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
405 clk->parent = parent;
408 /* --------------------------------------------------------------------
410 * -------------------------------------------------------------------- */
411 static struct resource sm_resource[] = {
413 NAMED_IRQ(19, "eim"),
415 NAMED_IRQ(21, "rtc"),
417 struct platform_device at32_sm_device = {
420 .resource = sm_resource,
421 .num_resources = ARRAY_SIZE(sm_resource),
423 static struct clk at32_sm_pclk = {
425 .dev = &at32_sm_device.dev,
427 .mode = pbb_clk_mode,
428 .get_rate = pbb_clk_get_rate,
433 static struct resource intc0_resource[] = {
436 struct platform_device at32_intc0_device = {
439 .resource = intc0_resource,
440 .num_resources = ARRAY_SIZE(intc0_resource),
442 DEV_CLK(pclk, at32_intc0, pbb, 1);
444 static struct clk ebi_clk = {
447 .mode = hsb_clk_mode,
448 .get_rate = hsb_clk_get_rate,
451 static struct clk hramc_clk = {
454 .mode = hsb_clk_mode,
455 .get_rate = hsb_clk_get_rate,
460 static struct resource smc0_resource[] = {
464 DEV_CLK(pclk, smc0, pbb, 13);
465 DEV_CLK(mck, smc0, hsb, 0);
467 static struct platform_device pdc_device = {
471 DEV_CLK(hclk, pdc, hsb, 4);
472 DEV_CLK(pclk, pdc, pba, 16);
474 static struct clk pico_clk = {
477 .mode = cpu_clk_mode,
478 .get_rate = cpu_clk_get_rate,
482 /* --------------------------------------------------------------------
484 * -------------------------------------------------------------------- */
486 static struct clk hmatrix_clk = {
487 .name = "hmatrix_clk",
489 .mode = pbb_clk_mode,
490 .get_rate = pbb_clk_get_rate,
494 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
496 #define hmatrix_readl(reg) \
497 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
498 #define hmatrix_writel(reg,value) \
499 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
502 * Set bits in the HMATRIX Special Function Register (SFR) used by the
503 * External Bus Interface (EBI). This can be used to enable special
504 * features like CompactFlash support, NAND Flash support, etc. on
505 * certain chipselects.
507 static inline void set_ebi_sfr_bits(u32 mask)
511 clk_enable(&hmatrix_clk);
512 sfr = hmatrix_readl(SFR4);
514 hmatrix_writel(SFR4, sfr);
515 clk_disable(&hmatrix_clk);
518 /* --------------------------------------------------------------------
519 * System Timer/Counter (TC)
520 * -------------------------------------------------------------------- */
521 static struct resource at32_systc0_resource[] = {
525 struct platform_device at32_systc0_device = {
528 .resource = at32_systc0_resource,
529 .num_resources = ARRAY_SIZE(at32_systc0_resource),
531 DEV_CLK(pclk, at32_systc0, pbb, 3);
533 /* --------------------------------------------------------------------
535 * -------------------------------------------------------------------- */
537 static struct resource pio0_resource[] = {
542 DEV_CLK(mck, pio0, pba, 10);
544 static struct resource pio1_resource[] = {
549 DEV_CLK(mck, pio1, pba, 11);
551 static struct resource pio2_resource[] = {
556 DEV_CLK(mck, pio2, pba, 12);
558 static struct resource pio3_resource[] = {
563 DEV_CLK(mck, pio3, pba, 13);
565 static struct resource pio4_resource[] = {
570 DEV_CLK(mck, pio4, pba, 14);
572 void __init at32_add_system_devices(void)
574 system_manager.eim_first_irq = EIM_IRQ_BASE;
576 platform_device_register(&at32_sm_device);
577 platform_device_register(&at32_intc0_device);
578 platform_device_register(&smc0_device);
579 platform_device_register(&pdc_device);
581 platform_device_register(&at32_systc0_device);
583 platform_device_register(&pio0_device);
584 platform_device_register(&pio1_device);
585 platform_device_register(&pio2_device);
586 platform_device_register(&pio3_device);
587 platform_device_register(&pio4_device);
590 /* --------------------------------------------------------------------
592 * -------------------------------------------------------------------- */
594 static struct atmel_uart_data atmel_usart0_data = {
598 static struct resource atmel_usart0_resource[] = {
602 DEFINE_DEV_DATA(atmel_usart, 0);
603 DEV_CLK(usart, atmel_usart0, pba, 4);
605 static struct atmel_uart_data atmel_usart1_data = {
609 static struct resource atmel_usart1_resource[] = {
613 DEFINE_DEV_DATA(atmel_usart, 1);
614 DEV_CLK(usart, atmel_usart1, pba, 4);
616 static struct atmel_uart_data atmel_usart2_data = {
620 static struct resource atmel_usart2_resource[] = {
624 DEFINE_DEV_DATA(atmel_usart, 2);
625 DEV_CLK(usart, atmel_usart2, pba, 5);
627 static struct atmel_uart_data atmel_usart3_data = {
631 static struct resource atmel_usart3_resource[] = {
635 DEFINE_DEV_DATA(atmel_usart, 3);
636 DEV_CLK(usart, atmel_usart3, pba, 6);
638 static inline void configure_usart0_pins(void)
640 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
641 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
644 static inline void configure_usart1_pins(void)
646 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
647 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
650 static inline void configure_usart2_pins(void)
652 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
653 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
656 static inline void configure_usart3_pins(void)
658 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
659 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
662 static struct platform_device *__initdata at32_usarts[4];
664 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
666 struct platform_device *pdev;
670 pdev = &atmel_usart0_device;
671 configure_usart0_pins();
674 pdev = &atmel_usart1_device;
675 configure_usart1_pins();
678 pdev = &atmel_usart2_device;
679 configure_usart2_pins();
682 pdev = &atmel_usart3_device;
683 configure_usart3_pins();
689 if (PXSEG(pdev->resource[0].start) == P4SEG) {
690 /* Addresses in the P4 segment are permanently mapped 1:1 */
691 struct atmel_uart_data *data = pdev->dev.platform_data;
692 data->regs = (void __iomem *)pdev->resource[0].start;
696 at32_usarts[line] = pdev;
699 struct platform_device *__init at32_add_device_usart(unsigned int id)
701 platform_device_register(at32_usarts[id]);
702 return at32_usarts[id];
705 struct platform_device *atmel_default_console_device;
707 void __init at32_setup_serial_console(unsigned int usart_id)
709 atmel_default_console_device = at32_usarts[usart_id];
712 /* --------------------------------------------------------------------
714 * -------------------------------------------------------------------- */
716 static struct eth_platform_data macb0_data;
717 static struct resource macb0_resource[] = {
721 DEFINE_DEV_DATA(macb, 0);
722 DEV_CLK(hclk, macb0, hsb, 8);
723 DEV_CLK(pclk, macb0, pbb, 6);
725 static struct eth_platform_data macb1_data;
726 static struct resource macb1_resource[] = {
730 DEFINE_DEV_DATA(macb, 1);
731 DEV_CLK(hclk, macb1, hsb, 9);
732 DEV_CLK(pclk, macb1, pbb, 7);
734 struct platform_device *__init
735 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
737 struct platform_device *pdev;
741 pdev = &macb0_device;
743 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
744 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
745 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
746 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
747 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
748 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
749 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
750 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
751 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
752 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
754 if (!data->is_rmii) {
755 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
756 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
757 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
758 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
759 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
760 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
761 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
762 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
763 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
768 pdev = &macb1_device;
770 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
771 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
772 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
773 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
774 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
775 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
776 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
777 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
778 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
779 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
781 if (!data->is_rmii) {
782 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
783 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
784 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
785 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
786 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
787 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
788 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
789 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
790 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
798 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
799 platform_device_register(pdev);
804 /* --------------------------------------------------------------------
806 * -------------------------------------------------------------------- */
807 static struct resource atmel_spi0_resource[] = {
811 DEFINE_DEV(atmel_spi, 0);
812 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
814 static struct resource atmel_spi1_resource[] = {
818 DEFINE_DEV(atmel_spi, 1);
819 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
822 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
823 unsigned int n, const u8 *pins)
825 unsigned int pin, mode;
827 for (; n; n--, b++) {
828 b->bus_num = bus_num;
829 if (b->chip_select >= 4)
831 pin = (unsigned)b->controller_data;
833 pin = pins[b->chip_select];
834 b->controller_data = (void *)pin;
836 mode = AT32_GPIOF_OUTPUT;
837 if (!(b->mode & SPI_CS_HIGH))
838 mode |= AT32_GPIOF_HIGH;
839 at32_select_gpio(pin, mode);
843 struct platform_device *__init
844 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
847 * Manage the chipselects as GPIOs, normally using the same pins
848 * the SPI controller expects; but boards can use other pins.
850 static u8 __initdata spi0_pins[] =
851 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
852 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
853 static u8 __initdata spi1_pins[] =
854 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
855 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
856 struct platform_device *pdev;
860 pdev = &atmel_spi0_device;
861 select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
862 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
863 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
864 at32_spi_setup_slaves(0, b, n, spi0_pins);
868 pdev = &atmel_spi1_device;
869 select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
870 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
871 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
872 at32_spi_setup_slaves(1, b, n, spi1_pins);
879 spi_register_board_info(b, n);
880 platform_device_register(pdev);
884 /* --------------------------------------------------------------------
886 * -------------------------------------------------------------------- */
887 static struct atmel_lcdfb_info atmel_lcdfb0_data;
888 static struct resource atmel_lcdfb0_resource[] = {
892 .flags = IORESOURCE_MEM,
896 /* Placeholder for pre-allocated fb memory */
902 DEFINE_DEV_DATA(atmel_lcdfb, 0);
903 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
904 static struct clk atmel_lcdfb0_pixclk = {
906 .dev = &atmel_lcdfb0_device.dev,
908 .get_rate = genclk_get_rate,
909 .set_rate = genclk_set_rate,
910 .set_parent = genclk_set_parent,
914 struct platform_device *__init
915 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
916 unsigned long fbmem_start, unsigned long fbmem_len)
918 struct platform_device *pdev;
919 struct atmel_lcdfb_info *info;
920 struct fb_monspecs *monspecs;
921 struct fb_videomode *modedb;
922 unsigned int modedb_size;
925 * Do a deep copy of the fb data, monspecs and modedb. Make
926 * sure all allocations are done before setting up the
929 monspecs = kmemdup(data->default_monspecs,
930 sizeof(struct fb_monspecs), GFP_KERNEL);
934 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
935 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
938 monspecs->modedb = modedb;
942 pdev = &atmel_lcdfb0_device;
943 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
944 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
945 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
946 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
947 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
948 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
949 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
950 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
951 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
952 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
953 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
954 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
955 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
956 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
957 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
958 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
959 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
960 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
961 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
962 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
963 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
964 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
965 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
966 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
967 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
968 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
969 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
970 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
971 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
972 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
973 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
975 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
976 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
984 pdev->resource[2].start = fbmem_start;
985 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
986 pdev->resource[2].flags = IORESOURCE_MEM;
989 info = pdev->dev.platform_data;
990 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
991 info->default_monspecs = monspecs;
993 platform_device_register(pdev);
1003 /* --------------------------------------------------------------------
1005 * -------------------------------------------------------------------- */
1006 static struct clk gclk0 = {
1008 .mode = genclk_mode,
1009 .get_rate = genclk_get_rate,
1010 .set_rate = genclk_set_rate,
1011 .set_parent = genclk_set_parent,
1014 static struct clk gclk1 = {
1016 .mode = genclk_mode,
1017 .get_rate = genclk_get_rate,
1018 .set_rate = genclk_set_rate,
1019 .set_parent = genclk_set_parent,
1022 static struct clk gclk2 = {
1024 .mode = genclk_mode,
1025 .get_rate = genclk_get_rate,
1026 .set_rate = genclk_set_rate,
1027 .set_parent = genclk_set_parent,
1030 static struct clk gclk3 = {
1032 .mode = genclk_mode,
1033 .get_rate = genclk_get_rate,
1034 .set_rate = genclk_set_rate,
1035 .set_parent = genclk_set_parent,
1038 static struct clk gclk4 = {
1040 .mode = genclk_mode,
1041 .get_rate = genclk_get_rate,
1042 .set_rate = genclk_set_rate,
1043 .set_parent = genclk_set_parent,
1047 struct clk *at32_clock_list[] = {
1073 &atmel_usart0_usart,
1074 &atmel_usart1_usart,
1075 &atmel_usart2_usart,
1076 &atmel_usart3_usart,
1081 &atmel_spi0_spi_clk,
1082 &atmel_spi1_spi_clk,
1084 &atmel_lcdfb0_pixclk,
1091 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1093 void __init at32_portmux_init(void)
1095 at32_init_pio(&pio0_device);
1096 at32_init_pio(&pio1_device);
1097 at32_init_pio(&pio2_device);
1098 at32_init_pio(&pio3_device);
1099 at32_init_pio(&pio4_device);
1102 void __init at32_clock_init(void)
1104 struct at32_sm *sm = &system_manager;
1105 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1108 if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
1113 if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
1114 pll0.parent = &osc1;
1115 if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
1116 pll1.parent = &osc1;
1118 genclk_init_parent(&gclk0);
1119 genclk_init_parent(&gclk1);
1120 genclk_init_parent(&gclk2);
1121 genclk_init_parent(&gclk3);
1122 genclk_init_parent(&gclk4);
1123 genclk_init_parent(&atmel_lcdfb0_pixclk);
1126 * Turn on all clocks that have at least one user already, and
1127 * turn off everything else. We only do this for module
1128 * clocks, and even though it isn't particularly pretty to
1129 * check the address of the mode function, it should do the
1132 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1133 struct clk *clk = at32_clock_list[i];
1135 if (clk->users == 0)
1138 if (clk->mode == &cpu_clk_mode)
1139 cpu_mask |= 1 << clk->index;
1140 else if (clk->mode == &hsb_clk_mode)
1141 hsb_mask |= 1 << clk->index;
1142 else if (clk->mode == &pba_clk_mode)
1143 pba_mask |= 1 << clk->index;
1144 else if (clk->mode == &pbb_clk_mode)
1145 pbb_mask |= 1 << clk->index;
1148 sm_writel(sm, PM_CPU_MASK, cpu_mask);
1149 sm_writel(sm, PM_HSB_MASK, hsb_mask);
1150 sm_writel(sm, PM_PBA_MASK, pba_mask);
1151 sm_writel(sm, PM_PBB_MASK, pbb_mask);