arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/fb.h>
  10 #include <linux/init.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/usb/atmel_usba_udc.h>
  15
  16 #include <asm/io.h>
  17 #include <asm/irq.h>
  18
  19 #include <asm/arch/at32ap700x.h>
  20 #include <asm/arch/board.h>
  21 #include <asm/arch/portmux.h>
  22
  23 #include <video/atmel_lcdc.h>
  24
  25 #include "clock.h"
  26 #include "hmatrix.h"
  27 #include "pio.h"
  28 #include "pm.h"
  29
  30
  31 #define PBMEM(base)                                     \
  32         {                                               \
  33                 .start          = base,                 \
  34                 .end            = base + 0x3ff,         \
  35                 .flags          = IORESOURCE_MEM,       \
  36         }
  37 #define IRQ(num)                                        \
  38         {                                               \
  39                 .start          = num,                  \
  40                 .end            = num,                  \
  41                 .flags          = IORESOURCE_IRQ,       \
  42         }
  43 #define NAMED_IRQ(num, _name)                           \
  44         {                                               \
  45                 .start          = num,                  \
  46                 .end            = num,                  \
  47                 .name           = _name,                \
  48                 .flags          = IORESOURCE_IRQ,       \
  49         }
  50
  51 /* REVISIT these assume *every* device supports DMA, but several
  52  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  53  */
  54 #define DEFINE_DEV(_name, _id)                                  \
  55 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  56 static struct platform_device _name##_id##_device = {           \
  57         .name           = #_name,                               \
  58         .id             = _id,                                  \
  59         .dev            = {                                     \
  60                 .dma_mask = &_name##_id##_dma_mask,             \
  61                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  62         },                                                      \
  63         .resource       = _name##_id##_resource,                \
  64         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  65 }
  66 #define DEFINE_DEV_DATA(_name, _id)                             \
  67 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  68 static struct platform_device _name##_id##_device = {           \
  69         .name           = #_name,                               \
  70         .id             = _id,                                  \
  71         .dev            = {                                     \
  72                 .dma_mask = &_name##_id##_dma_mask,             \
  73                 .platform_data  = &_name##_id##_data,           \
  74                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  75         },                                                      \
  76         .resource       = _name##_id##_resource,                \
  77         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  78 }
  79
  80 #define select_peripheral(pin, periph, flags)                   \
  81         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  82
  83 #define DEV_CLK(_name, devname, bus, _index)                    \
  84 static struct clk devname##_##_name = {                         \
  85         .name           = #_name,                               \
  86         .dev            = &devname##_device.dev,                \
  87         .parent         = &bus##_clk,                           \
  88         .mode           = bus##_clk_mode,                       \
  89         .get_rate       = bus##_clk_get_rate,                   \
  90         .index          = _index,                               \
  91 }
  92
  93 static DEFINE_SPINLOCK(pm_lock);
  94
  95 unsigned long at32ap7000_osc_rates[3] = {
  96         [0] = 32768,
  97         /* FIXME: these are ATSTK1002-specific */
  98         [1] = 20000000,
  99         [2] = 12000000,
 100 };
 101
 102 static unsigned long osc_get_rate(struct clk *clk)
 103 {
 104         return at32ap7000_osc_rates[clk->index];
 105 }
 106
 107 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 108 {
 109         unsigned long div, mul, rate;
 110
 111         if (!(control & PM_BIT(PLLEN)))
 112                 return 0;
 113
 114         div = PM_BFEXT(PLLDIV, control) + 1;
 115         mul = PM_BFEXT(PLLMUL, control) + 1;
 116
 117         rate = clk->parent->get_rate(clk->parent);
 118         rate = (rate + div / 2) / div;
 119         rate *= mul;
 120
 121         return rate;
 122 }
 123
 124 static unsigned long pll0_get_rate(struct clk *clk)
 125 {
 126         u32 control;
 127
 128         control = pm_readl(PLL0);
 129
 130         return pll_get_rate(clk, control);
 131 }
 132
 133 static unsigned long pll1_get_rate(struct clk *clk)
 134 {
 135         u32 control;
 136
 137         control = pm_readl(PLL1);
 138
 139         return pll_get_rate(clk, control);
 140 }
 141
 142 /*
 143  * The AT32AP7000 has five primary clock sources: One 32kHz
 144  * oscillator, two crystal oscillators and two PLLs.
 145  */
 146 static struct clk osc32k = {
 147         .name           = "osc32k",
 148         .get_rate       = osc_get_rate,
 149         .users          = 1,
 150         .index          = 0,
 151 };
 152 static struct clk osc0 = {
 153         .name           = "osc0",
 154         .get_rate       = osc_get_rate,
 155         .users          = 1,
 156         .index          = 1,
 157 };
 158 static struct clk osc1 = {
 159         .name           = "osc1",
 160         .get_rate       = osc_get_rate,
 161         .index          = 2,
 162 };
 163 static struct clk pll0 = {
 164         .name           = "pll0",
 165         .get_rate       = pll0_get_rate,
 166         .parent         = &osc0,
 167 };
 168 static struct clk pll1 = {
 169         .name           = "pll1",
 170         .get_rate       = pll1_get_rate,
 171         .parent         = &osc0,
 172 };
 173
 174 /*
 175  * The main clock can be either osc0 or pll0.  The boot loader may
 176  * have chosen one for us, so we don't really know which one until we
 177  * have a look at the SM.
 178  */
 179 static struct clk *main_clock;
 180
 181 /*
 182  * Synchronous clocks are generated from the main clock. The clocks
 183  * must satisfy the constraint
 184  *   fCPU >= fHSB >= fPB
 185  * i.e. each clock must not be faster than its parent.
 186  */
 187 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 188 {
 189         return main_clock->get_rate(main_clock) >> shift;
 190 };
 191
 192 static void cpu_clk_mode(struct clk *clk, int enabled)
 193 {
 194         unsigned long flags;
 195         u32 mask;
 196
 197         spin_lock_irqsave(&pm_lock, flags);
 198         mask = pm_readl(CPU_MASK);
 199         if (enabled)
 200                 mask |= 1 << clk->index;
 201         else
 202                 mask &= ~(1 << clk->index);
 203         pm_writel(CPU_MASK, mask);
 204         spin_unlock_irqrestore(&pm_lock, flags);
 205 }
 206
 207 static unsigned long cpu_clk_get_rate(struct clk *clk)
 208 {
 209         unsigned long cksel, shift = 0;
 210
 211         cksel = pm_readl(CKSEL);
 212         if (cksel & PM_BIT(CPUDIV))
 213                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 214
 215         return bus_clk_get_rate(clk, shift);
 216 }
 217
 218 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 219 {
 220         u32 control;
 221         unsigned long parent_rate, child_div, actual_rate, div;
 222
 223         parent_rate = clk->parent->get_rate(clk->parent);
 224         control = pm_readl(CKSEL);
 225
 226         if (control & PM_BIT(HSBDIV))
 227                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 228         else
 229                 child_div = 1;
 230
 231         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 232                 actual_rate = parent_rate;
 233                 control &= ~PM_BIT(CPUDIV);
 234         } else {
 235                 unsigned int cpusel;
 236                 div = (parent_rate + rate / 2) / rate;
 237                 if (div > child_div)
 238                         div = child_div;
 239                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 240                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 241                 actual_rate = parent_rate / (1 << (cpusel + 1));
 242         }
 243
 244         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 245                         clk->name, rate, actual_rate);
 246
 247         if (apply)
 248                 pm_writel(CKSEL, control);
 249
 250         return actual_rate;
 251 }
 252
 253 static void hsb_clk_mode(struct clk *clk, int enabled)
 254 {
 255         unsigned long flags;
 256         u32 mask;
 257
 258         spin_lock_irqsave(&pm_lock, flags);
 259         mask = pm_readl(HSB_MASK);
 260         if (enabled)
 261                 mask |= 1 << clk->index;
 262         else
 263                 mask &= ~(1 << clk->index);
 264         pm_writel(HSB_MASK, mask);
 265         spin_unlock_irqrestore(&pm_lock, flags);
 266 }
 267
 268 static unsigned long hsb_clk_get_rate(struct clk *clk)
 269 {
 270         unsigned long cksel, shift = 0;
 271
 272         cksel = pm_readl(CKSEL);
 273         if (cksel & PM_BIT(HSBDIV))
 274                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 275
 276         return bus_clk_get_rate(clk, shift);
 277 }
 278
 279 static void pba_clk_mode(struct clk *clk, int enabled)
 280 {
 281         unsigned long flags;
 282         u32 mask;
 283
 284         spin_lock_irqsave(&pm_lock, flags);
 285         mask = pm_readl(PBA_MASK);
 286         if (enabled)
 287                 mask |= 1 << clk->index;
 288         else
 289                 mask &= ~(1 << clk->index);
 290         pm_writel(PBA_MASK, mask);
 291         spin_unlock_irqrestore(&pm_lock, flags);
 292 }
 293
 294 static unsigned long pba_clk_get_rate(struct clk *clk)
 295 {
 296         unsigned long cksel, shift = 0;
 297
 298         cksel = pm_readl(CKSEL);
 299         if (cksel & PM_BIT(PBADIV))
 300                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 301
 302         return bus_clk_get_rate(clk, shift);
 303 }
 304
 305 static void pbb_clk_mode(struct clk *clk, int enabled)
 306 {
 307         unsigned long flags;
 308         u32 mask;
 309
 310         spin_lock_irqsave(&pm_lock, flags);
 311         mask = pm_readl(PBB_MASK);
 312         if (enabled)
 313                 mask |= 1 << clk->index;
 314         else
 315                 mask &= ~(1 << clk->index);
 316         pm_writel(PBB_MASK, mask);
 317         spin_unlock_irqrestore(&pm_lock, flags);
 318 }
 319
 320 static unsigned long pbb_clk_get_rate(struct clk *clk)
 321 {
 322         unsigned long cksel, shift = 0;
 323
 324         cksel = pm_readl(CKSEL);
 325         if (cksel & PM_BIT(PBBDIV))
 326                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 327
 328         return bus_clk_get_rate(clk, shift);
 329 }
 330
 331 static struct clk cpu_clk = {
 332         .name           = "cpu",
 333         .get_rate       = cpu_clk_get_rate,
 334         .set_rate       = cpu_clk_set_rate,
 335         .users          = 1,
 336 };
 337 static struct clk hsb_clk = {
 338         .name           = "hsb",
 339         .parent         = &cpu_clk,
 340         .get_rate       = hsb_clk_get_rate,
 341 };
 342 static struct clk pba_clk = {
 343         .name           = "pba",
 344         .parent         = &hsb_clk,
 345         .mode           = hsb_clk_mode,
 346         .get_rate       = pba_clk_get_rate,
 347         .index          = 1,
 348 };
 349 static struct clk pbb_clk = {
 350         .name           = "pbb",
 351         .parent         = &hsb_clk,
 352         .mode           = hsb_clk_mode,
 353         .get_rate       = pbb_clk_get_rate,
 354         .users          = 1,
 355         .index          = 2,
 356 };
 357
 358 /* --------------------------------------------------------------------
 359  *  Generic Clock operations
 360  * -------------------------------------------------------------------- */
 361
 362 static void genclk_mode(struct clk *clk, int enabled)
 363 {
 364         u32 control;
 365
 366         control = pm_readl(GCCTRL(clk->index));
 367         if (enabled)
 368                 control |= PM_BIT(CEN);
 369         else
 370                 control &= ~PM_BIT(CEN);
 371         pm_writel(GCCTRL(clk->index), control);
 372 }
 373
 374 static unsigned long genclk_get_rate(struct clk *clk)
 375 {
 376         u32 control;
 377         unsigned long div = 1;
 378
 379         control = pm_readl(GCCTRL(clk->index));
 380         if (control & PM_BIT(DIVEN))
 381                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 382
 383         return clk->parent->get_rate(clk->parent) / div;
 384 }
 385
 386 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 387 {
 388         u32 control;
 389         unsigned long parent_rate, actual_rate, div;
 390
 391         parent_rate = clk->parent->get_rate(clk->parent);
 392         control = pm_readl(GCCTRL(clk->index));
 393
 394         if (rate > 3 * parent_rate / 4) {
 395                 actual_rate = parent_rate;
 396                 control &= ~PM_BIT(DIVEN);
 397         } else {
 398                 div = (parent_rate + rate) / (2 * rate) - 1;
 399                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 400                 actual_rate = parent_rate / (2 * (div + 1));
 401         }
 402
 403         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 404                 clk->name, rate, actual_rate);
 405
 406         if (apply)
 407                 pm_writel(GCCTRL(clk->index), control);
 408
 409         return actual_rate;
 410 }
 411
 412 int genclk_set_parent(struct clk *clk, struct clk *parent)
 413 {
 414         u32 control;
 415
 416         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 417                 clk->name, parent->name, clk->parent->name);
 418
 419         control = pm_readl(GCCTRL(clk->index));
 420
 421         if (parent == &osc1 || parent == &pll1)
 422                 control |= PM_BIT(OSCSEL);
 423         else if (parent == &osc0 || parent == &pll0)
 424                 control &= ~PM_BIT(OSCSEL);
 425         else
 426                 return -EINVAL;
 427
 428         if (parent == &pll0 || parent == &pll1)
 429                 control |= PM_BIT(PLLSEL);
 430         else
 431                 control &= ~PM_BIT(PLLSEL);
 432
 433         pm_writel(GCCTRL(clk->index), control);
 434         clk->parent = parent;
 435
 436         return 0;
 437 }
 438
 439 static void __init genclk_init_parent(struct clk *clk)
 440 {
 441         u32 control;
 442         struct clk *parent;
 443
 444         BUG_ON(clk->index > 7);
 445
 446         control = pm_readl(GCCTRL(clk->index));
 447         if (control & PM_BIT(OSCSEL))
 448                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 449         else
 450                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 451
 452         clk->parent = parent;
 453 }
 454
 455 /* --------------------------------------------------------------------
 456  *  System peripherals
 457  * -------------------------------------------------------------------- */
 458 static struct resource at32_pm0_resource[] = {
 459         {
 460                 .start  = 0xfff00000,
 461                 .end    = 0xfff0007f,
 462                 .flags  = IORESOURCE_MEM,
 463         },
 464         IRQ(20),
 465 };
 466
 467 static struct resource at32ap700x_rtc0_resource[] = {
 468         {
 469                 .start  = 0xfff00080,
 470                 .end    = 0xfff000af,
 471                 .flags  = IORESOURCE_MEM,
 472         },
 473         IRQ(21),
 474 };
 475
 476 static struct resource at32_wdt0_resource[] = {
 477         {
 478                 .start  = 0xfff000b0,
 479                 .end    = 0xfff000cf,
 480                 .flags  = IORESOURCE_MEM,
 481         },
 482 };
 483
 484 static struct resource at32_eic0_resource[] = {
 485         {
 486                 .start  = 0xfff00100,
 487                 .end    = 0xfff0013f,
 488                 .flags  = IORESOURCE_MEM,
 489         },
 490         IRQ(19),
 491 };
 492
 493 DEFINE_DEV(at32_pm, 0);
 494 DEFINE_DEV(at32ap700x_rtc, 0);
 495 DEFINE_DEV(at32_wdt, 0);
 496 DEFINE_DEV(at32_eic, 0);
 497
 498 /*
 499  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 500  * is always running.
 501  */
 502 static struct clk at32_pm_pclk = {
 503         .name           = "pclk",
 504         .dev            = &at32_pm0_device.dev,
 505         .parent         = &pbb_clk,
 506         .mode           = pbb_clk_mode,
 507         .get_rate       = pbb_clk_get_rate,
 508         .users          = 1,
 509         .index          = 0,
 510 };
 511
 512 static struct resource intc0_resource[] = {
 513         PBMEM(0xfff00400),
 514 };
 515 struct platform_device at32_intc0_device = {
 516         .name           = "intc",
 517         .id             = 0,
 518         .resource       = intc0_resource,
 519         .num_resources  = ARRAY_SIZE(intc0_resource),
 520 };
 521 DEV_CLK(pclk, at32_intc0, pbb, 1);
 522
 523 static struct clk ebi_clk = {
 524         .name           = "ebi",
 525         .parent         = &hsb_clk,
 526         .mode           = hsb_clk_mode,
 527         .get_rate       = hsb_clk_get_rate,
 528         .users          = 1,
 529 };
 530 static struct clk hramc_clk = {
 531         .name           = "hramc",
 532         .parent         = &hsb_clk,
 533         .mode           = hsb_clk_mode,
 534         .get_rate       = hsb_clk_get_rate,
 535         .users          = 1,
 536         .index          = 3,
 537 };
 538
 539 static struct resource smc0_resource[] = {
 540         PBMEM(0xfff03400),
 541 };
 542 DEFINE_DEV(smc, 0);
 543 DEV_CLK(pclk, smc0, pbb, 13);
 544 DEV_CLK(mck, smc0, hsb, 0);
 545
 546 static struct platform_device pdc_device = {
 547         .name           = "pdc",
 548         .id             = 0,
 549 };
 550 DEV_CLK(hclk, pdc, hsb, 4);
 551 DEV_CLK(pclk, pdc, pba, 16);
 552
 553 static struct clk pico_clk = {
 554         .name           = "pico",
 555         .parent         = &cpu_clk,
 556         .mode           = cpu_clk_mode,
 557         .get_rate       = cpu_clk_get_rate,
 558         .users          = 1,
 559 };
 560
 561 static struct resource dmaca0_resource[] = {
 562         {
 563                 .start  = 0xff200000,
 564                 .end    = 0xff20ffff,
 565                 .flags  = IORESOURCE_MEM,
 566         },
 567         IRQ(2),
 568 };
 569 DEFINE_DEV(dmaca, 0);
 570 DEV_CLK(hclk, dmaca0, hsb, 10);
 571
 572 /* --------------------------------------------------------------------
 573  * HMATRIX
 574  * -------------------------------------------------------------------- */
 575
 576 static struct clk hmatrix_clk = {
 577         .name           = "hmatrix_clk",
 578         .parent         = &pbb_clk,
 579         .mode           = pbb_clk_mode,
 580         .get_rate       = pbb_clk_get_rate,
 581         .index          = 2,
 582         .users          = 1,
 583 };
 584 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 585
 586 #define hmatrix_readl(reg)                                      \
 587         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 588 #define hmatrix_writel(reg,value)                               \
 589         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 590
 591 /*
 592  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 593  * External Bus Interface (EBI). This can be used to enable special
 594  * features like CompactFlash support, NAND Flash support, etc. on
 595  * certain chipselects.
 596  */
 597 static inline void set_ebi_sfr_bits(u32 mask)
 598 {
 599         u32 sfr;
 600
 601         clk_enable(&hmatrix_clk);
 602         sfr = hmatrix_readl(SFR4);
 603         sfr |= mask;
 604         hmatrix_writel(SFR4, sfr);
 605         clk_disable(&hmatrix_clk);
 606 }
 607
 608 /* --------------------------------------------------------------------
 609  *  System Timer/Counter (TC)
 610  * -------------------------------------------------------------------- */
 611 static struct resource at32_systc0_resource[] = {
 612         PBMEM(0xfff00c00),
 613         IRQ(22),
 614 };
 615 struct platform_device at32_systc0_device = {
 616         .name           = "systc",
 617         .id             = 0,
 618         .resource       = at32_systc0_resource,
 619         .num_resources  = ARRAY_SIZE(at32_systc0_resource),
 620 };
 621 DEV_CLK(pclk, at32_systc0, pbb, 3);
 622
 623 /* --------------------------------------------------------------------
 624  *  PIO
 625  * -------------------------------------------------------------------- */
 626
 627 static struct resource pio0_resource[] = {
 628         PBMEM(0xffe02800),
 629         IRQ(13),
 630 };
 631 DEFINE_DEV(pio, 0);
 632 DEV_CLK(mck, pio0, pba, 10);
 633
 634 static struct resource pio1_resource[] = {
 635         PBMEM(0xffe02c00),
 636         IRQ(14),
 637 };
 638 DEFINE_DEV(pio, 1);
 639 DEV_CLK(mck, pio1, pba, 11);
 640
 641 static struct resource pio2_resource[] = {
 642         PBMEM(0xffe03000),
 643         IRQ(15),
 644 };
 645 DEFINE_DEV(pio, 2);
 646 DEV_CLK(mck, pio2, pba, 12);
 647
 648 static struct resource pio3_resource[] = {
 649         PBMEM(0xffe03400),
 650         IRQ(16),
 651 };
 652 DEFINE_DEV(pio, 3);
 653 DEV_CLK(mck, pio3, pba, 13);
 654
 655 static struct resource pio4_resource[] = {
 656         PBMEM(0xffe03800),
 657         IRQ(17),
 658 };
 659 DEFINE_DEV(pio, 4);
 660 DEV_CLK(mck, pio4, pba, 14);
 661
 662 void __init at32_add_system_devices(void)
 663 {
 664         platform_device_register(&at32_pm0_device);
 665         platform_device_register(&at32_intc0_device);
 666         platform_device_register(&at32ap700x_rtc0_device);
 667         platform_device_register(&at32_wdt0_device);
 668         platform_device_register(&at32_eic0_device);
 669         platform_device_register(&smc0_device);
 670         platform_device_register(&pdc_device);
 671         platform_device_register(&dmaca0_device);
 672
 673         platform_device_register(&at32_systc0_device);
 674
 675         platform_device_register(&pio0_device);
 676         platform_device_register(&pio1_device);
 677         platform_device_register(&pio2_device);
 678         platform_device_register(&pio3_device);
 679         platform_device_register(&pio4_device);
 680 }
 681
 682 /* --------------------------------------------------------------------
 683  *  USART
 684  * -------------------------------------------------------------------- */
 685
 686 static struct atmel_uart_data atmel_usart0_data = {
 687         .use_dma_tx     = 1,
 688         .use_dma_rx     = 1,
 689 };
 690 static struct resource atmel_usart0_resource[] = {
 691         PBMEM(0xffe00c00),
 692         IRQ(6),
 693 };
 694 DEFINE_DEV_DATA(atmel_usart, 0);
 695 DEV_CLK(usart, atmel_usart0, pba, 3);
 696
 697 static struct atmel_uart_data atmel_usart1_data = {
 698         .use_dma_tx     = 1,
 699         .use_dma_rx     = 1,
 700 };
 701 static struct resource atmel_usart1_resource[] = {
 702         PBMEM(0xffe01000),
 703         IRQ(7),
 704 };
 705 DEFINE_DEV_DATA(atmel_usart, 1);
 706 DEV_CLK(usart, atmel_usart1, pba, 4);
 707
 708 static struct atmel_uart_data atmel_usart2_data = {
 709         .use_dma_tx     = 1,
 710         .use_dma_rx     = 1,
 711 };
 712 static struct resource atmel_usart2_resource[] = {
 713         PBMEM(0xffe01400),
 714         IRQ(8),
 715 };
 716 DEFINE_DEV_DATA(atmel_usart, 2);
 717 DEV_CLK(usart, atmel_usart2, pba, 5);
 718
 719 static struct atmel_uart_data atmel_usart3_data = {
 720         .use_dma_tx     = 1,
 721         .use_dma_rx     = 1,
 722 };
 723 static struct resource atmel_usart3_resource[] = {
 724         PBMEM(0xffe01800),
 725         IRQ(9),
 726 };
 727 DEFINE_DEV_DATA(atmel_usart, 3);
 728 DEV_CLK(usart, atmel_usart3, pba, 6);
 729
 730 static inline void configure_usart0_pins(void)
 731 {
 732         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 733         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 734 }
 735
 736 static inline void configure_usart1_pins(void)
 737 {
 738         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 739         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 740 }
 741
 742 static inline void configure_usart2_pins(void)
 743 {
 744         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 745         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 746 }
 747
 748 static inline void configure_usart3_pins(void)
 749 {
 750         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 751         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 752 }
 753
 754 static struct platform_device *__initdata at32_usarts[4];
 755
 756 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 757 {
 758         struct platform_device *pdev;
 759
 760         switch (hw_id) {
 761         case 0:
 762                 pdev = &atmel_usart0_device;
 763                 configure_usart0_pins();
 764                 break;
 765         case 1:
 766                 pdev = &atmel_usart1_device;
 767                 configure_usart1_pins();
 768                 break;
 769         case 2:
 770                 pdev = &atmel_usart2_device;
 771                 configure_usart2_pins();
 772                 break;
 773         case 3:
 774                 pdev = &atmel_usart3_device;
 775                 configure_usart3_pins();
 776                 break;
 777         default:
 778                 return;
 779         }
 780
 781         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 782                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 783                 struct atmel_uart_data *data = pdev->dev.platform_data;
 784                 data->regs = (void __iomem *)pdev->resource[0].start;
 785         }
 786
 787         pdev->id = line;
 788         at32_usarts[line] = pdev;
 789 }
 790
 791 struct platform_device *__init at32_add_device_usart(unsigned int id)
 792 {
 793         platform_device_register(at32_usarts[id]);
 794         return at32_usarts[id];
 795 }
 796
 797 struct platform_device *atmel_default_console_device;
 798
 799 void __init at32_setup_serial_console(unsigned int usart_id)
 800 {
 801         atmel_default_console_device = at32_usarts[usart_id];
 802 }
 803
 804 /* --------------------------------------------------------------------
 805  *  Ethernet
 806  * -------------------------------------------------------------------- */
 807
 808 #ifdef CONFIG_CPU_AT32AP7000
 809 static struct eth_platform_data macb0_data;
 810 static struct resource macb0_resource[] = {
 811         PBMEM(0xfff01800),
 812         IRQ(25),
 813 };
 814 DEFINE_DEV_DATA(macb, 0);
 815 DEV_CLK(hclk, macb0, hsb, 8);
 816 DEV_CLK(pclk, macb0, pbb, 6);
 817
 818 static struct eth_platform_data macb1_data;
 819 static struct resource macb1_resource[] = {
 820         PBMEM(0xfff01c00),
 821         IRQ(26),
 822 };
 823 DEFINE_DEV_DATA(macb, 1);
 824 DEV_CLK(hclk, macb1, hsb, 9);
 825 DEV_CLK(pclk, macb1, pbb, 7);
 826
 827 struct platform_device *__init
 828 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 829 {
 830         struct platform_device *pdev;
 831
 832         switch (id) {
 833         case 0:
 834                 pdev = &macb0_device;
 835
 836                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 837                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 838                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
 839                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
 840                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
 841                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
 842                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
 843                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
 844                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
 845                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
 846
 847                 if (!data->is_rmii) {
 848                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
 849                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
 850                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
 851                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
 852                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
 853                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
 854                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
 855                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
 856                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
 857                 }
 858                 break;
 859
 860         case 1:
 861                 pdev = &macb1_device;
 862
 863                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
 864                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
 865                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
 866                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
 867                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
 868                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
 869                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
 870                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
 871                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
 872                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
 873
 874                 if (!data->is_rmii) {
 875                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
 876                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
 877                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
 878                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
 879                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
 880                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
 881                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
 882                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
 883                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
 884                 }
 885                 break;
 886
 887         default:
 888                 return NULL;
 889         }
 890
 891         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
 892         platform_device_register(pdev);
 893
 894         return pdev;
 895 }
 896 #endif
 897
 898 /* --------------------------------------------------------------------
 899  *  SPI
 900  * -------------------------------------------------------------------- */
 901 static struct resource atmel_spi0_resource[] = {
 902         PBMEM(0xffe00000),
 903         IRQ(3),
 904 };
 905 DEFINE_DEV(atmel_spi, 0);
 906 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
 907
 908 static struct resource atmel_spi1_resource[] = {
 909         PBMEM(0xffe00400),
 910         IRQ(4),
 911 };
 912 DEFINE_DEV(atmel_spi, 1);
 913 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
 914
 915 static void __init
 916 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
 917                       unsigned int n, const u8 *pins)
 918 {
 919         unsigned int pin, mode;
 920
 921         for (; n; n--, b++) {
 922                 b->bus_num = bus_num;
 923                 if (b->chip_select >= 4)
 924                         continue;
 925                 pin = (unsigned)b->controller_data;
 926                 if (!pin) {
 927                         pin = pins[b->chip_select];
 928                         b->controller_data = (void *)pin;
 929                 }
 930                 mode = AT32_GPIOF_OUTPUT;
 931                 if (!(b->mode & SPI_CS_HIGH))
 932                         mode |= AT32_GPIOF_HIGH;
 933                 at32_select_gpio(pin, mode);
 934         }
 935 }
 936
 937 struct platform_device *__init
 938 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 939 {
 940         /*
 941          * Manage the chipselects as GPIOs, normally using the same pins
 942          * the SPI controller expects; but boards can use other pins.
 943          */
 944         static u8 __initdata spi0_pins[] =
 945                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
 946                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
 947         static u8 __initdata spi1_pins[] =
 948                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
 949                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
 950         struct platform_device *pdev;
 951
 952         switch (id) {
 953         case 0:
 954                 pdev = &atmel_spi0_device;
 955                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
 956                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
 957                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
 958                 at32_spi_setup_slaves(0, b, n, spi0_pins);
 959                 break;
 960
 961         case 1:
 962                 pdev = &atmel_spi1_device;
 963                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
 964                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
 965                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
 966                 at32_spi_setup_slaves(1, b, n, spi1_pins);
 967                 break;
 968
 969         default:
 970                 return NULL;
 971         }
 972
 973         spi_register_board_info(b, n);
 974         platform_device_register(pdev);
 975         return pdev;
 976 }
 977
 978 /* --------------------------------------------------------------------
 979  *  TWI
 980  * -------------------------------------------------------------------- */
 981 static struct resource atmel_twi0_resource[] __initdata = {
 982         PBMEM(0xffe00800),
 983         IRQ(5),
 984 };
 985 static struct clk atmel_twi0_pclk = {
 986         .name           = "twi_pclk",
 987         .parent         = &pba_clk,
 988         .mode           = pba_clk_mode,
 989         .get_rate       = pba_clk_get_rate,
 990         .index          = 2,
 991 };
 992
 993 struct platform_device *__init at32_add_device_twi(unsigned int id)
 994 {
 995         struct platform_device *pdev;
 996
 997         if (id != 0)
 998                 return NULL;
 999
1000         pdev = platform_device_alloc("atmel_twi", id);
1001         if (!pdev)
1002                 return NULL;
1003
1004         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1005                                 ARRAY_SIZE(atmel_twi0_resource)))
1006                 goto err_add_resources;
1007
1008         select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1009         select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1010
1011         atmel_twi0_pclk.dev = &pdev->dev;
1012
1013         platform_device_add(pdev);
1014         return pdev;
1015
1016 err_add_resources:
1017         platform_device_put(pdev);
1018         return NULL;
1019 }
1020
1021 /* --------------------------------------------------------------------
1022  * MMC
1023  * -------------------------------------------------------------------- */
1024 static struct resource atmel_mci0_resource[] __initdata = {
1025         PBMEM(0xfff02400),
1026         IRQ(28),
1027 };
1028 static struct clk atmel_mci0_pclk = {
1029         .name           = "mci_clk",
1030         .parent         = &pbb_clk,
1031         .mode           = pbb_clk_mode,
1032         .get_rate       = pbb_clk_get_rate,
1033         .index          = 9,
1034 };
1035
1036 struct platform_device *__init at32_add_device_mci(unsigned int id)
1037 {
1038         struct platform_device *pdev;
1039
1040         if (id != 0)
1041                 return NULL;
1042
1043         pdev = platform_device_alloc("atmel_mci", id);
1044         if (!pdev)
1045                 return NULL;
1046
1047         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1048                                 ARRAY_SIZE(atmel_mci0_resource)))
1049                 goto err_add_resources;
1050
1051         select_peripheral(PA(10), PERIPH_A, 0); /* CLK   */
1052         select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1053         select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1054         select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1055         select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1056         select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1057
1058         atmel_mci0_pclk.dev = &pdev->dev;
1059
1060         platform_device_add(pdev);
1061         return pdev;
1062
1063 err_add_resources:
1064         platform_device_put(pdev);
1065         return NULL;
1066 }
1067
1068 /* --------------------------------------------------------------------
1069  *  LCDC
1070  * -------------------------------------------------------------------- */
1071 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1072 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1073 static struct resource atmel_lcdfb0_resource[] = {
1074         {
1075                 .start          = 0xff000000,
1076                 .end            = 0xff000fff,
1077                 .flags          = IORESOURCE_MEM,
1078         },
1079         IRQ(1),
1080         {
1081                 /* Placeholder for pre-allocated fb memory */
1082                 .start          = 0x00000000,
1083                 .end            = 0x00000000,
1084                 .flags          = 0,
1085         },
1086 };
1087 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1088 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1089 static struct clk atmel_lcdfb0_pixclk = {
1090         .name           = "lcdc_clk",
1091         .dev            = &atmel_lcdfb0_device.dev,
1092         .mode           = genclk_mode,
1093         .get_rate       = genclk_get_rate,
1094         .set_rate       = genclk_set_rate,
1095         .set_parent     = genclk_set_parent,
1096         .index          = 7,
1097 };
1098
1099 struct platform_device *__init
1100 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1101                      unsigned long fbmem_start, unsigned long fbmem_len)
1102 {
1103         struct platform_device *pdev;
1104         struct atmel_lcdfb_info *info;
1105         struct fb_monspecs *monspecs;
1106         struct fb_videomode *modedb;
1107         unsigned int modedb_size;
1108
1109         /*
1110          * Do a deep copy of the fb data, monspecs and modedb. Make
1111          * sure all allocations are done before setting up the
1112          * portmux.
1113          */
1114         monspecs = kmemdup(data->default_monspecs,
1115                            sizeof(struct fb_monspecs), GFP_KERNEL);
1116         if (!monspecs)
1117                 return NULL;
1118
1119         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1120         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1121         if (!modedb)
1122                 goto err_dup_modedb;
1123         monspecs->modedb = modedb;
1124
1125         switch (id) {
1126         case 0:
1127                 pdev = &atmel_lcdfb0_device;
1128                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1129                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1130                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1131                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1132                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1133                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1134                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1135                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1136                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1137                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1138                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1139                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1140                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1141                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1142                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1143                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1144                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1145                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1146                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1147                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1148                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1149                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1150                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1151                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1152                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1153                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1154                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1155                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1156                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1157                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1158                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1159
1160                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1161                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1162                 break;
1163
1164         default:
1165                 goto err_invalid_id;
1166         }
1167
1168         if (fbmem_len) {
1169                 pdev->resource[2].start = fbmem_start;
1170                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1171                 pdev->resource[2].flags = IORESOURCE_MEM;
1172         }
1173
1174         info = pdev->dev.platform_data;
1175         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1176         info->default_monspecs = monspecs;
1177
1178         platform_device_register(pdev);
1179         return pdev;
1180
1181 err_invalid_id:
1182         kfree(modedb);
1183 err_dup_modedb:
1184         kfree(monspecs);
1185         return NULL;
1186 }
1187 #endif
1188
1189 /* --------------------------------------------------------------------
1190  *  PWM
1191  * -------------------------------------------------------------------- */
1192 static struct resource atmel_pwm0_resource[] __initdata = {
1193         PBMEM(0xfff01400),
1194         IRQ(24),
1195 };
1196 static struct clk atmel_pwm0_mck = {
1197         .name           = "mck",
1198         .parent         = &pbb_clk,
1199         .mode           = pbb_clk_mode,
1200         .get_rate       = pbb_clk_get_rate,
1201         .index          = 5,
1202 };
1203
1204 struct platform_device *__init at32_add_device_pwm(u32 mask)
1205 {
1206         struct platform_device *pdev;
1207
1208         if (!mask)
1209                 return NULL;
1210
1211         pdev = platform_device_alloc("atmel_pwm", 0);
1212         if (!pdev)
1213                 return NULL;
1214
1215         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1216                                 ARRAY_SIZE(atmel_pwm0_resource)))
1217                 goto out_free_pdev;
1218
1219         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1220                 goto out_free_pdev;
1221
1222         if (mask & (1 << 0))
1223                 select_peripheral(PA(28), PERIPH_A, 0);
1224         if (mask & (1 << 1))
1225                 select_peripheral(PA(29), PERIPH_A, 0);
1226         if (mask & (1 << 2))
1227                 select_peripheral(PA(21), PERIPH_B, 0);
1228         if (mask & (1 << 3))
1229                 select_peripheral(PA(22), PERIPH_B, 0);
1230
1231         atmel_pwm0_mck.dev = &pdev->dev;
1232
1233         platform_device_add(pdev);
1234
1235         return pdev;
1236
1237 out_free_pdev:
1238         platform_device_put(pdev);
1239         return NULL;
1240 }
1241
1242 /* --------------------------------------------------------------------
1243  *  SSC
1244  * -------------------------------------------------------------------- */
1245 static struct resource ssc0_resource[] = {
1246         PBMEM(0xffe01c00),
1247         IRQ(10),
1248 };
1249 DEFINE_DEV(ssc, 0);
1250 DEV_CLK(pclk, ssc0, pba, 7);
1251
1252 static struct resource ssc1_resource[] = {
1253         PBMEM(0xffe02000),
1254         IRQ(11),
1255 };
1256 DEFINE_DEV(ssc, 1);
1257 DEV_CLK(pclk, ssc1, pba, 8);
1258
1259 static struct resource ssc2_resource[] = {
1260         PBMEM(0xffe02400),
1261         IRQ(12),
1262 };
1263 DEFINE_DEV(ssc, 2);
1264 DEV_CLK(pclk, ssc2, pba, 9);
1265
1266 struct platform_device *__init
1267 at32_add_device_ssc(unsigned int id, unsigned int flags)
1268 {
1269         struct platform_device *pdev;
1270
1271         switch (id) {
1272         case 0:
1273                 pdev = &ssc0_device;
1274                 if (flags & ATMEL_SSC_RF)
1275                         select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1276                 if (flags & ATMEL_SSC_RK)
1277                         select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1278                 if (flags & ATMEL_SSC_TK)
1279                         select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1280                 if (flags & ATMEL_SSC_TF)
1281                         select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1282                 if (flags & ATMEL_SSC_TD)
1283                         select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1284                 if (flags & ATMEL_SSC_RD)
1285                         select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1286                 break;
1287         case 1:
1288                 pdev = &ssc1_device;
1289                 if (flags & ATMEL_SSC_RF)
1290                         select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1291                 if (flags & ATMEL_SSC_RK)
1292                         select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1293                 if (flags & ATMEL_SSC_TK)
1294                         select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1295                 if (flags & ATMEL_SSC_TF)
1296                         select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1297                 if (flags & ATMEL_SSC_TD)
1298                         select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1299                 if (flags & ATMEL_SSC_RD)
1300                         select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1301                 break;
1302         case 2:
1303                 pdev = &ssc2_device;
1304                 if (flags & ATMEL_SSC_TD)
1305                         select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1306                 if (flags & ATMEL_SSC_RD)
1307                         select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1308                 if (flags & ATMEL_SSC_TK)
1309                         select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1310                 if (flags & ATMEL_SSC_TF)
1311                         select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1312                 if (flags & ATMEL_SSC_RF)
1313                         select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1314                 if (flags & ATMEL_SSC_RK)
1315                         select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1316                 break;
1317         default:
1318                 return NULL;
1319         }
1320
1321         platform_device_register(pdev);
1322         return pdev;
1323 }
1324
1325 /* --------------------------------------------------------------------
1326  *  USB Device Controller
1327  * -------------------------------------------------------------------- */
1328 static struct resource usba0_resource[] __initdata = {
1329         {
1330                 .start          = 0xff300000,
1331                 .end            = 0xff3fffff,
1332                 .flags          = IORESOURCE_MEM,
1333         }, {
1334                 .start          = 0xfff03000,
1335                 .end            = 0xfff033ff,
1336                 .flags          = IORESOURCE_MEM,
1337         },
1338         IRQ(31),
1339 };
1340 static struct clk usba0_pclk = {
1341         .name           = "pclk",
1342         .parent         = &pbb_clk,
1343         .mode           = pbb_clk_mode,
1344         .get_rate       = pbb_clk_get_rate,
1345         .index          = 12,
1346 };
1347 static struct clk usba0_hclk = {
1348         .name           = "hclk",
1349         .parent         = &hsb_clk,
1350         .mode           = hsb_clk_mode,
1351         .get_rate       = hsb_clk_get_rate,
1352         .index          = 6,
1353 };
1354
1355 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1356         [idx] = {                                               \
1357                 .name           = nam,                          \
1358                 .index          = idx,                          \
1359                 .fifo_size      = maxpkt,                       \
1360                 .nr_banks       = maxbk,                        \
1361                 .can_dma        = dma,                          \
1362                 .can_isoc       = isoc,                         \
1363         }
1364
1365 static struct usba_ep_data at32_usba_ep[] __initdata = {
1366         EP("ep0",     0,   64, 1, 0, 0),
1367         EP("ep1",     1,  512, 2, 1, 1),
1368         EP("ep2",     2,  512, 2, 1, 1),
1369         EP("ep3-int", 3,   64, 3, 1, 0),
1370         EP("ep4-int", 4,   64, 3, 1, 0),
1371         EP("ep5",     5, 1024, 3, 1, 1),
1372         EP("ep6",     6, 1024, 3, 1, 1),
1373 };
1374
1375 #undef EP
1376
1377 struct platform_device *__init
1378 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1379 {
1380         /*
1381          * pdata doesn't have room for any endpoints, so we need to
1382          * append room for the ones we need right after it.
1383          */
1384         struct {
1385                 struct usba_platform_data pdata;
1386                 struct usba_ep_data ep[7];
1387         } usba_data;
1388         struct platform_device *pdev;
1389
1390         if (id != 0)
1391                 return NULL;
1392
1393         pdev = platform_device_alloc("atmel_usba_udc", 0);
1394         if (!pdev)
1395                 return NULL;
1396
1397         if (platform_device_add_resources(pdev, usba0_resource,
1398                                           ARRAY_SIZE(usba0_resource)))
1399                 goto out_free_pdev;
1400
1401         if (data)
1402                 usba_data.pdata.vbus_pin = data->vbus_pin;
1403         else
1404                 usba_data.pdata.vbus_pin = -EINVAL;
1405
1406         data = &usba_data.pdata;
1407         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1408         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1409
1410         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1411                 goto out_free_pdev;
1412
1413         if (data->vbus_pin >= 0)
1414                 at32_select_gpio(data->vbus_pin, 0);
1415
1416         usba0_pclk.dev = &pdev->dev;
1417         usba0_hclk.dev = &pdev->dev;
1418
1419         platform_device_add(pdev);
1420
1421         return pdev;
1422
1423 out_free_pdev:
1424         platform_device_put(pdev);
1425         return NULL;
1426 }
1427
1428 /* --------------------------------------------------------------------
1429  * IDE / CompactFlash
1430  * -------------------------------------------------------------------- */
1431 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1432 static struct resource at32_smc_cs4_resource[] __initdata = {
1433         {
1434                 .start  = 0x04000000,
1435                 .end    = 0x07ffffff,
1436                 .flags  = IORESOURCE_MEM,
1437         },
1438         IRQ(~0UL), /* Magic IRQ will be overridden */
1439 };
1440 static struct resource at32_smc_cs5_resource[] __initdata = {
1441         {
1442                 .start  = 0x20000000,
1443                 .end    = 0x23ffffff,
1444                 .flags  = IORESOURCE_MEM,
1445         },
1446         IRQ(~0UL), /* Magic IRQ will be overridden */
1447 };
1448
1449 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1450                 unsigned int cs, unsigned int extint)
1451 {
1452         static unsigned int extint_pin_map[4] __initdata = {
1453                 GPIO_PIN_PB(25),
1454                 GPIO_PIN_PB(26),
1455                 GPIO_PIN_PB(27),
1456                 GPIO_PIN_PB(28),
1457         };
1458         static bool common_pins_initialized __initdata = false;
1459         unsigned int extint_pin;
1460         int ret;
1461
1462         if (extint >= ARRAY_SIZE(extint_pin_map))
1463                 return -EINVAL;
1464         extint_pin = extint_pin_map[extint];
1465
1466         switch (cs) {
1467         case 4:
1468                 ret = platform_device_add_resources(pdev,
1469                                 at32_smc_cs4_resource,
1470                                 ARRAY_SIZE(at32_smc_cs4_resource));
1471                 if (ret)
1472                         return ret;
1473
1474                 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1475                 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1476                 break;
1477         case 5:
1478                 ret = platform_device_add_resources(pdev,
1479                                 at32_smc_cs5_resource,
1480                                 ARRAY_SIZE(at32_smc_cs5_resource));
1481                 if (ret)
1482                         return ret;
1483
1484                 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1485                 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1486                 break;
1487         default:
1488                 return -EINVAL;
1489         }
1490
1491         if (!common_pins_initialized) {
1492                 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1493                 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1494                 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1495                 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1496                 common_pins_initialized = true;
1497         }
1498
1499         at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1500
1501         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1502         pdev->resource[1].end = pdev->resource[1].start;
1503
1504         return 0;
1505 }
1506
1507 struct platform_device *__init
1508 at32_add_device_ide(unsigned int id, unsigned int extint,
1509                     struct ide_platform_data *data)
1510 {
1511         struct platform_device *pdev;
1512
1513         pdev = platform_device_alloc("at32_ide", id);
1514         if (!pdev)
1515                 goto fail;
1516
1517         if (platform_device_add_data(pdev, data,
1518                                 sizeof(struct ide_platform_data)))
1519                 goto fail;
1520
1521         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1522                 goto fail;
1523
1524         platform_device_add(pdev);
1525         return pdev;
1526
1527 fail:
1528         platform_device_put(pdev);
1529         return NULL;
1530 }
1531
1532 struct platform_device *__init
1533 at32_add_device_cf(unsigned int id, unsigned int extint,
1534                     struct cf_platform_data *data)
1535 {
1536         struct platform_device *pdev;
1537
1538         pdev = platform_device_alloc("at32_cf", id);
1539         if (!pdev)
1540                 goto fail;
1541
1542         if (platform_device_add_data(pdev, data,
1543                                 sizeof(struct cf_platform_data)))
1544                 goto fail;
1545
1546         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1547                 goto fail;
1548
1549         if (data->detect_pin != GPIO_PIN_NONE)
1550                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1551         if (data->reset_pin != GPIO_PIN_NONE)
1552                 at32_select_gpio(data->reset_pin, 0);
1553         if (data->vcc_pin != GPIO_PIN_NONE)
1554                 at32_select_gpio(data->vcc_pin, 0);
1555         /* READY is used as extint, so we can't select it as gpio */
1556
1557         platform_device_add(pdev);
1558         return pdev;
1559
1560 fail:
1561         platform_device_put(pdev);
1562         return NULL;
1563 }
1564 #endif
1565
1566 /* --------------------------------------------------------------------
1567  * AC97C
1568  * -------------------------------------------------------------------- */
1569 static struct resource atmel_ac97c0_resource[] __initdata = {
1570         PBMEM(0xfff02800),
1571         IRQ(29),
1572 };
1573 static struct clk atmel_ac97c0_pclk = {
1574         .name           = "pclk",
1575         .parent         = &pbb_clk,
1576         .mode           = pbb_clk_mode,
1577         .get_rate       = pbb_clk_get_rate,
1578         .index          = 10,
1579 };
1580
1581 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1582 {
1583         struct platform_device *pdev;
1584
1585         if (id != 0)
1586                 return NULL;
1587
1588         pdev = platform_device_alloc("atmel_ac97c", id);
1589         if (!pdev)
1590                 return NULL;
1591
1592         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1593                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1594                 goto err_add_resources;
1595
1596         select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1597         select_peripheral(PB(21), PERIPH_B, 0); /* SDO  */
1598         select_peripheral(PB(22), PERIPH_B, 0); /* SDI  */
1599         select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1600
1601         atmel_ac97c0_pclk.dev = &pdev->dev;
1602
1603         platform_device_add(pdev);
1604         return pdev;
1605
1606 err_add_resources:
1607         platform_device_put(pdev);
1608         return NULL;
1609 }
1610
1611 /* --------------------------------------------------------------------
1612  * ABDAC
1613  * -------------------------------------------------------------------- */
1614 static struct resource abdac0_resource[] __initdata = {
1615         PBMEM(0xfff02000),
1616         IRQ(27),
1617 };
1618 static struct clk abdac0_pclk = {
1619         .name           = "pclk",
1620         .parent         = &pbb_clk,
1621         .mode           = pbb_clk_mode,
1622         .get_rate       = pbb_clk_get_rate,
1623         .index          = 8,
1624 };
1625 static struct clk abdac0_sample_clk = {
1626         .name           = "sample_clk",
1627         .mode           = genclk_mode,
1628         .get_rate       = genclk_get_rate,
1629         .set_rate       = genclk_set_rate,
1630         .set_parent     = genclk_set_parent,
1631         .index          = 6,
1632 };
1633
1634 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1635 {
1636         struct platform_device *pdev;
1637
1638         if (id != 0)
1639                 return NULL;
1640
1641         pdev = platform_device_alloc("abdac", id);
1642         if (!pdev)
1643                 return NULL;
1644
1645         if (platform_device_add_resources(pdev, abdac0_resource,
1646                                 ARRAY_SIZE(abdac0_resource)))
1647                 goto err_add_resources;
1648
1649         select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
1650         select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
1651         select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
1652         select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
1653
1654         abdac0_pclk.dev = &pdev->dev;
1655         abdac0_sample_clk.dev = &pdev->dev;
1656
1657         platform_device_add(pdev);
1658         return pdev;
1659
1660 err_add_resources:
1661         platform_device_put(pdev);
1662         return NULL;
1663 }
1664
1665 /* --------------------------------------------------------------------
1666  *  GCLK
1667  * -------------------------------------------------------------------- */
1668 static struct clk gclk0 = {
1669         .name           = "gclk0",
1670         .mode           = genclk_mode,
1671         .get_rate       = genclk_get_rate,
1672         .set_rate       = genclk_set_rate,
1673         .set_parent     = genclk_set_parent,
1674         .index          = 0,
1675 };
1676 static struct clk gclk1 = {
1677         .name           = "gclk1",
1678         .mode           = genclk_mode,
1679         .get_rate       = genclk_get_rate,
1680         .set_rate       = genclk_set_rate,
1681         .set_parent     = genclk_set_parent,
1682         .index          = 1,
1683 };
1684 static struct clk gclk2 = {
1685         .name           = "gclk2",
1686         .mode           = genclk_mode,
1687         .get_rate       = genclk_get_rate,
1688         .set_rate       = genclk_set_rate,
1689         .set_parent     = genclk_set_parent,
1690         .index          = 2,
1691 };
1692 static struct clk gclk3 = {
1693         .name           = "gclk3",
1694         .mode           = genclk_mode,
1695         .get_rate       = genclk_get_rate,
1696         .set_rate       = genclk_set_rate,
1697         .set_parent     = genclk_set_parent,
1698         .index          = 3,
1699 };
1700 static struct clk gclk4 = {
1701         .name           = "gclk4",
1702         .mode           = genclk_mode,
1703         .get_rate       = genclk_get_rate,
1704         .set_rate       = genclk_set_rate,
1705         .set_parent     = genclk_set_parent,
1706         .index          = 4,
1707 };
1708
1709 struct clk *at32_clock_list[] = {
1710         &osc32k,
1711         &osc0,
1712         &osc1,
1713         &pll0,
1714         &pll1,
1715         &cpu_clk,
1716         &hsb_clk,
1717         &pba_clk,
1718         &pbb_clk,
1719         &at32_pm_pclk,
1720         &at32_intc0_pclk,
1721         &hmatrix_clk,
1722         &ebi_clk,
1723         &hramc_clk,
1724         &smc0_pclk,
1725         &smc0_mck,
1726         &pdc_hclk,
1727         &pdc_pclk,
1728         &dmaca0_hclk,
1729         &pico_clk,
1730         &pio0_mck,
1731         &pio1_mck,
1732         &pio2_mck,
1733         &pio3_mck,
1734         &pio4_mck,
1735         &at32_systc0_pclk,
1736         &atmel_usart0_usart,
1737         &atmel_usart1_usart,
1738         &atmel_usart2_usart,
1739         &atmel_usart3_usart,
1740         &atmel_pwm0_mck,
1741 #if defined(CONFIG_CPU_AT32AP7000)
1742         &macb0_hclk,
1743         &macb0_pclk,
1744         &macb1_hclk,
1745         &macb1_pclk,
1746 #endif
1747         &atmel_spi0_spi_clk,
1748         &atmel_spi1_spi_clk,
1749         &atmel_twi0_pclk,
1750         &atmel_mci0_pclk,
1751 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1752         &atmel_lcdfb0_hck1,
1753         &atmel_lcdfb0_pixclk,
1754 #endif
1755         &ssc0_pclk,
1756         &ssc1_pclk,
1757         &ssc2_pclk,
1758         &usba0_hclk,
1759         &usba0_pclk,
1760         &atmel_ac97c0_pclk,
1761         &abdac0_pclk,
1762         &abdac0_sample_clk,
1763         &gclk0,
1764         &gclk1,
1765         &gclk2,
1766         &gclk3,
1767         &gclk4,
1768 };
1769 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1770
1771 void __init at32_portmux_init(void)
1772 {
1773         at32_init_pio(&pio0_device);
1774         at32_init_pio(&pio1_device);
1775         at32_init_pio(&pio2_device);
1776         at32_init_pio(&pio3_device);
1777         at32_init_pio(&pio4_device);
1778 }
1779
1780 void __init at32_clock_init(void)
1781 {
1782         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1783         int i;
1784
1785         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
1786                 main_clock = &pll0;
1787                 cpu_clk.parent = &pll0;
1788         } else {
1789                 main_clock = &osc0;
1790                 cpu_clk.parent = &osc0;
1791         }
1792
1793         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1794                 pll0.parent = &osc1;
1795         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1796                 pll1.parent = &osc1;
1797
1798         genclk_init_parent(&gclk0);
1799         genclk_init_parent(&gclk1);
1800         genclk_init_parent(&gclk2);
1801         genclk_init_parent(&gclk3);
1802         genclk_init_parent(&gclk4);
1803 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1804         genclk_init_parent(&atmel_lcdfb0_pixclk);
1805 #endif
1806         genclk_init_parent(&abdac0_sample_clk);
1807
1808         /*
1809          * Turn on all clocks that have at least one user already, and
1810          * turn off everything else. We only do this for module
1811          * clocks, and even though it isn't particularly pretty to
1812          * check the address of the mode function, it should do the
1813          * trick...
1814          */
1815         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1816                 struct clk *clk = at32_clock_list[i];
1817
1818                 if (clk->users == 0)
1819                         continue;
1820
1821                 if (clk->mode == &cpu_clk_mode)
1822                         cpu_mask |= 1 << clk->index;
1823                 else if (clk->mode == &hsb_clk_mode)
1824                         hsb_mask |= 1 << clk->index;
1825                 else if (clk->mode == &pba_clk_mode)
1826                         pba_mask |= 1 << clk->index;
1827                 else if (clk->mode == &pbb_clk_mode)
1828                         pbb_mask |= 1 << clk->index;
1829         }
1830
1831         pm_writel(CPU_MASK, cpu_mask);
1832         pm_writel(HSB_MASK, hsb_mask);
1833         pm_writel(PBA_MASK, pba_mask);
1834         pm_writel(PBB_MASK, pbb_mask);
1835 }